參數(shù)資料
型號： ADUC834
廠商： Analog Devices, Inc.
英文描述： MicroConverter, Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
中文描述： MicroConverter的，雙與嵌入62KB閃存MCU 16-/24-位ADC
文件頁數(shù)： 55/72頁
文件大?。?/td> 1451K
代理商： ADUC834
REV.
P
rC (12 March 2002)
ADuC834
–
55
–
PRELIMINARY TECHNICAL DATA
T MOD
SFR Address
Power-On Default Value
Bit Addressable
T imer/C ounter 0 and 1 Mode Register
89H
00H
No
T able X X VI. T MOD SFR Bit Designations
Bit
Name
Description
7
Gate
T imer 1 Gating Control.
Set
by software to enable timer/counter 1 only while
INT 1
pin is high and T R1 control bit is set.
Cleared
by software to enable timer 1 whenever T R1 control bit is set.
T imer 1 T imer or Counter Select Bit.
Set
by software to select counter operation (input from T 1 pin).
Cleared
by software to select timer operation (input from internal system clock).
T imer 1 Mode Select Bit 1 (Used with M0 Bit).
T imer 1 Mode Select Bit 0.
M1
M0
0
0
T H1 operates as an 8-bit timer/counter. T L1 serves as 5-bit prescaler.
0
1
16-Bit T imer/Counter. T H1 and T L1 are cascaded; there is no prescaler.
1
0
8-Bit Auto-Reload T imer/Counter. T H1 holds a value which is to be
reloaded into T L1 each time it overflows.
1
1
T imer/Counter 1 Stopped.
T imer 0 Gating Control.
Set
by software to enable timer/counter 0 only while
INT 0
pin is high and T R0 control bit is set.
Cleared
by software to enable T imer 0 whenever T R0 control bit is set.
T imer 0 T imer or Counter Select Bit.
Set
by software to select counter operation (input from T 0 pin).
Cleared
by software to select timer operation (input from internal system clock).
T imer 0 Mode Select Bit 1.
T imer 0 Mode Select Bit 0.
M1
M0
0
0
T H0 operates as an 8-bit timer/counter. T L0 serves as 5-bit prescaler.
0
1
16-Bit T imer/Counter. T H0 and T L0 are cascaded; there is no prescaler
1
0
8-Bit Auto-Reload T imer/Counter. T H0 holds a value which is to be
reloaded into T L0 each time it overflows.
1
1
T L0 is an 8-bit timer/counter controlled by the standard timer 0 control
bits. T H0 is an 8-bit timer only, controlled by T imer 1 control bits.
6
C/
T
5
4
M1
M0
3
Gate
2
C/
T
1
0
M1
M0
T IME RS/C OUNT E RS
T he ADuC 834 has three 16-bit T imer/C ounters: T imer 0,
T imer 1, and T imer 2. T he T imer/Counter hardware has been
included on-chip to relieve the processor core of the over-
head inherent in implementing timer/counter functionality
in software. Each T imer/Counter consists of two 8-bit registers
T Hx and T Lx (x = 0, 1 and 2). All three can be configured to
operate either as timers or event counters.
In
‘
T imer
’
function, the T Lx register is incremented every ma-
chine cycle. T hus one can think of it as counting machine cycles.
Since a machine cycle consists of 12 core clock periods, the
maximum count rate is 1/12 of the core clock frequency.
In
‘
Counter
’
function, the T Lx register is incremented by a 1-to-
0 transition at its corresponding external input pin, T 0, T 1, or
T 2. In this function, the external input is sampled during
S5P2 of every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is
incremented. T he new count value appears in the register during
S3P1 of the cycle following the one in which the transition was
detected. Since it takes two machine cycles (16 core clock periods)
to recognize a 1-to-0 transition, the maximum count rate is 1/16
of the core clock frequency. T here are no restrictions on the
duty cycle of the external input signal, but to ensure that a
given level is sampled at least once before it changes, it must be
held for a minimum of one full machine cycle. Remember that
the core clock frequency is programmed via the CD0
–
2 selec-
tion bits in the PLLCON SFR.
User configuration and control of the timers is achieved via
three main SFRs. T MOD and T CON control the configura-
tion of timers 0 and 1 while T 2CON configures timer 2.
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