參數(shù)資料
型號： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 88/112頁
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標準包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 77 of 112
ANALOG FRONT END DESCRIPTION AND OPERATION
6dB
0.5V
CCDIN
CLI
DIGITAL
FILTER
CLPOB
OPTICAL BLACK
CLAMP
12-BIT
ADC
DAC
CDS
VGA
INTERNAL
VREF
DCBYP
2V
FULL
SCALE
PRECISION
TIMING
GENERATOR
SHP
SHD
OUTPUT
DATA
LATCH
REFT
REFB
V-H
TIMING
GENERATION
SHP SHD
DOUTPHASE
CLPOB
PBLK
0.4V
1.4V
AD9920A
0.1F
CLAMP LEVEL
REGISTER
12
PBLK
–3dB, 0dB,
+3dB, +6dB
PBLK
SHP
AVDD
DC RESTORE
S11
S21
BLANK TO
ZERO OR
CLAMP LEVEL
1S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.
CDS GAIN
REGISTER
VD
HD
D0 TO D11
DOUTPHASE
DCLK
MODE
FIXED
DELAY
CLI
1
0
1
DCLKINV
DOUTDELAY
0
68
78
-10
0
Figure 100. Analog Front End Functional Block Diagram
The AD9920A signal processing chain is shown in Figure 100.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
DC Restore
Correlated Double Sampler (CDS)
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.3 V (AVDD 0.5 V), making it compatible
with the 1.8 V core supply voltage of the AD9920A. The dc
restore switch is active during the SHP sample pulse time.
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The timing
shown in Figure 23 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and data level of the CCD signal, respectively. The place-
ment of the SHP and SHD sampling edges is determined by the
setting of the SHPLOC and SHDLOC registers located at
Address 0x38. Placement of these two clock signals is critical
for achieving the best performance from the CCD.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of AFE Register
Address 0x00 controls whether the dc restore is active during
the PBLK interval.
The CDS gain is variable in four steps by using AFE Register
Address 0x04: 3 dB, 0 dB, +3 dB, and +6 dB. Improved noise
performance results from using the +3 dB setting, but the input
range is reduced (see the Analog Specifications section).
Analog Preblanking (PBLK)
During certain CCD blanking or substrate clocking intervals, the
CCD input signal to the AD9920A may increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. While
PBLK is active (low), the CDS input is internally shorted to
ground. It is recommended that PBLK be used to protect the
CDS input during the horizontal blanking and/or when the
SUBCK output is toggled.
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