- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1988 > AD9920ABBCZRL (Analog Devices Inc)IC PROCESSOR CCD 12BIT 105CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標(biāo)準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
AD9920A
Rev. B | Page 19 of 112
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9920A
features on-chip output drivers for the RG, HL, and H1 to H8
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG current can be adjusted for
optimum rise/fall time for a particular load by using the drive
strength control registers (Address 0x36 and Address 0x37). The
3-bit drive setting for each H1 to H8 output is adjustable in
4.3 mA increments: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.3 mA, 5 = 21.6 mA, 6 = 25.9 mA, and 7 = 30.2 mA.
The 3-bit drive settings for the HL and RG outputs are also
adjustable in 4.3 mA increments, but with a maximum drive
strength of 17.3 mA: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 4.3 mA, 5 = 8.6 mA, 6 = 12.9 mA, and 7 = 17.3 mA.
As shown in Figure 19, when HCLK Mode 1 is used, the H2,
H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7
outputs. Using the HCLKMODE register (Address 0x24,
Bits[4:0]), it is possible to select a different configuration.
Table 10 shows a comparison of the different programmable
settings for HCLK Mode 2 and HCLK Mode 3, respectively.
It is recommended that all H1 to H8 outputs on the AD9920A be
used together for maximum flexibility in drive strength settings.
A typical CCD with H1 and H2 inputs should have only the
AD9920A H1, H3, H5, and H7 outputs connected together to
drive the CCD H1 and should have only the AD9920A H2, H4,
H6, and H8 outputs connected together to drive the CCD H2.
In 3-phase HCLK mode, only six of the HCLK outputs are used,
with two outputs driving each of the three phases:
H1 and H2 are connected to CCD Phase 1.
H5 and H6 are connected to CCD Phase 2.
H7 and H8 are connected to CCD Phase 3.
Table 9. Timing Core Register Parameters for H1, H2, HL, RG, SHP, and SHD
Parameter
Length (Bits)
Range
Description
Positive Edge
6
0 to 63 edge location
Positive edge location for H1, H2, HL, H3P1, and RG.
Negative Edge
6
0 to 63 edge location
Negative edge location for H1, H2, HL, H3P1, and RG.
Sampling Location
6
0 to 63 edge location
Sampling location for internal SHP and SHD signals.
Drive Strength
3
0 to 7 current steps
Drive current for H1 to H8, HL, and RG outputs (4.3 mA per step).
Table 10. HCLK Modes, Selected by Address 0x24, Bits[4:0]
HCLKMODE
Register Value
Description
Mode 1
0x01
H1 edges are programmable with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1.
Mode 2
0x02
H1 edges are programmable with H3 = H5 = H7 = H1.
H2 edges are programmable with H4 = H6 = H8 = H2.
Mode 3
0x04
H1 edges are programmable with H3 = H1 and H2 = H4 = inverse of H1.
H5 edges are programmable with H7 = H5 and H6 = H8 = inverse of H5.
3-Phase Mode
0x10
H1 edges are programmable using Address 0x33 and H2 = H1 (Phase 1).
H5 edges are programmable using Address 0x31 and H6 = H5 (Phase 2).
H7 edges are programmable using Address 0x30 and H8 = H7 (Phase 3).
Invalid Selection
All other values
Invalid register settings. Do not use.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9978BCPZRL | IC PROCESSOR CCD 14BIT 40-LFCSP |
| ADADC71KD | IC ADC 16BIT HIGH RES 32-CDIP |
| ADADC80-Z-12 | IC ADC 12BIT INTEGRATED 32-CDIP |
| ADATE207BBPZ | IC TIMING FORMATTER QUAD 256BGA |
| ADC0804LCN | IC ADC 8-BIT 10KSPS 1LSB 20-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9921BBCZ | 制造商:Analog Devices 功能描述: |
| AD9921BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9923A | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。