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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 33 of 112
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each XV1 to XV24 output signal. Table 14 summarizes the
registers available for generating each V-pattern group. The first,
second, third, and fourth toggle positions (VTOG1, VTOG2,
VTOG3, and VTOG4) are the pixel locations within the line
where the pulse transitions. All toggle positions are 13-bit
values, allowing their placement anywhere in the first 8191
pixels of the line.
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the V-pattern
group within the line; VLEN designates the total length of the
V-pattern group, which determines the number of pixels between
each of the pattern repetitions when repetitions are used.
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART
value plus the toggle position.
When the selected V-output is designated as a VSG pulse, either
the VTOG1/VTOG2 or VTOG3/VTOG4 pair is selected using
V-Sequence Address 0x03, VSGPATSEL. All four toggle positions
are not simultaneously available for VSG pulses.
All unused V-channels must have their toggle positions
programmed to either 0 or maximum value. This prevents
unpredictable behavior because the default values of the
V-pattern group registers are unknown.
Table 14. Vertical Pattern Group Registers
Register
Length (Bits)
Description
VTOG1
13
First toggle position within the line for each XV1 to XV24 output, relative to VSTART value.
VTOG2
13
Second toggle position, relative to VSTART value.
VTOG3
13
Third toggle position, relative to VSTART value.
VTOG4
13
Fourth toggle position, relative to VSTART value.
HD
XV1
4
1
2
3
XV2
1
23
XV24
1
2
3
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
PROGRAMMABLE SETTINGS:
1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
06
87
8-
04
1
Figure 42. Vertical Pattern Group Programmability
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相關(guān)代理商/技術(shù)參數(shù) |
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