參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 55/112頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 47 of 112
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than the 13-bit V-pattern
toggle position counter. In general, the 13-bit toggle position
counter can be used with the sweep mode feature to support
very wide pulses; however, multiplier mode can be used to
generate even wider pulses.
The start polarity and toggle positions are still used in the same
manner as in the standard V-pattern group programming, but
VLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
VTOG2, VTOG3, and VTOG4) of the V-pattern group, the
VLEN is multiplied by the VTOG position to allow very long
pulses to be generated.
To calculate the exact toggle position, which is counted in pixels
after the start position, use the following equation:
Multiplier Mode Toggle Position = VTOG × VLEN
Because the VTOG register is multiplied by VLEN, the resolu-
tion of the toggle position placement is reduced. If VLEN = 4,
the toggle position precision is reduced to four-pixel increments
instead of to single-pixel increments. Table 20 summarizes how
the V-pattern group registers are used in multiplier mode opera-
tion. In multiplier mode, the VREP registers must always be
programmed to the same value as the highest toggle position.
Figure 59 illustrates this operation. The first toggle position is 2,
and the second toggle position is 9. In nonmultiplier mode, this
causes the V-sequence to toggle at Pixel 2 and then at Pixel 9
within a single HD line. However, in multiplier mode, toggle
positions are multiplied by the value of VLEN (in this case, 4);
therefore, the first toggle occurs at Pixel 8, and the second toggle
occurs at Pixel 36. Sweep mode is also enabled to allow the
toggle positions to cross the HD line boundaries.
Table 20. Multiplier Mode Register Parameters
Register
Length (Bits)
Range
Description
MULT_SWEEPx
1
High/low
High enables multiplier mode.
VPOL
1
High/low
Starting polarity of XV1 to XV24 signals in each V-pattern group.
VTOG
13
0 to 8191 pixel
location
Toggle positions for XV1 to XV24 signals in each V-pattern group.
VLEN
13
0 to 8191 pixels
Used as multiplier factor for toggle position counter.
VREP
13
0 to 8191 pixel
location
With VREP_MODE = 0, VREP_EVEN must be set to the same value as the highest VTOG
value. VREP_ODD and VREPA can be set to 0.
XV1 TO XV24
HD
VLEN
12
341
2341
234
1234
123
4123
412
3412
341
2341
234
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
PIXEL
NUMBER
12
345
6789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
55
4
1
2
4
2
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1START POLARITY (STARTPOL = 0).
2FIRST, SECOND, AND THIRD TOGGLE POSITIONS (VTOG1 = 2, VTOG2 = 9).
3LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG × VLEN).
5IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDARIES, AS SHOWN ABOVE.
0
68
78
-05
8
Figure 59. Example of Multiplier Region for Wide Vertical Pulse Timing
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