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參數(shù)資料
| 型號： | AD9978BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 14BIT 40-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 通道數(shù)： | 2 |
| 電壓 - 電源，模擬： | 1.8V |
| 電壓 - 電源，數(shù)字： | 1.8V |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9978BCPZRLDKR |
Dual-Channel, 14-Bit CCD Signal
Processor with Precision Timing Core
AD9978
Rev. SpB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Dual AFE channels
1.8 V analog and digital core supply voltage
Serial data output with reduced range LVDS outputs
Differential analog inputs
CDS or SHA configuration (CDS bypass) with
3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Precision Timing core with 240 ps resolution @ 65 MHz
APPLICATIONS
Digital video cameras
Digital still cameras
Digital copiers
Multifunction printers
High speed industrial cameras
GENERAL DESCRIPTION
The AD9978 is a highly integrated, dual-channel CCD signal
processor for high speed digital video camera applications. Each
channel is specified at pixel rates of up to 65 MHz and consists of
a complete analog front end with ADC conversion. The Precision
Timing core allows adjustment of the correlated double sampler
(CDS) and sample-and-hold amplifier (SHA) clocks with 240 ps
resolution at 65 MHz operation. The AD9978 also contains a
reduced range, low voltage differential signaling (LVDS) interface
for the dual-channel data outputs.
Each analog front end includes black level clamping, a CDS,
a VGA, and a 65 MHz, 14-bit ADC. Operation is programmed
using a 3-wire serial interface.
Packaged in a space-saving, 6 mm × 6 mm, 40-lead LFCSP, the
AD9978 is specified over an operating temperature range of
25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
INP_A
INM_A
INM_B
INP_B
–3dB, 0dB, +3dB, +6dB
CDS/
SHA
VGA
6dB TO 42dB
CLAMP
ADC
VD
HD
SDATA
SCK
CLI
CLK_OUT
DOUT0P
DOUT0N
DOUT1P
DOUT1N
DOUT2P
DOUT2N
DOUT3P
DOUT3N
TCLKP
TCLKN
SL
CLAMP
VREF
ADC
6dB TO 42dB
CDS/
SHA
VGA
PRECISION
TIMING
CORE
SYNC
GENERATOR
INTERNAL CLOCKS
INTERNAL
REGISTERS
LVDS
SERIALIZER
AD9978
0
68
10
-00
1
Figure 1.
For more information about the AD9978, contact Analog Devices via email at afe.ccd@analog.com.
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| AD9980/PCBZ | 功能描述:KIT EVALUATION AD9980 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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