參數(shù)資料
型號(hào): AD9920ABBCZRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 100/112頁(yè)
文件大?。?/td> 0K
描述: IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
電壓 - 電源,模擬: 1.6 V ~ 2 V
電壓 - 電源,數(shù)字: 1.6 V ~ 2 V
封裝/外殼: 105-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 105-CSPBGA(8x8)
包裝: 帶卷 (TR)
AD9920A
Rev. B | Page 88 of 112
CIRCUIT LAYOUT INFORMATION
The PCB layout is critical in achieving good image quality from
the AD9920A. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD pins, must be decoupled to
ground with good quality, high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. If possible, there should be a 4.7 μF
or larger value bypass capacitor for each main supply—AVDD,
HVDD, and DRVDD—although this is not necessary for each
individual pin. In most applications, the supply for RGVDD and
HVDD is shared, which can be done as long as the individual
supply pins are separately bypassed with 0.1 μF capacitors. A
separate 3 V supply can also be used for DRVDD, but this supply
pin should still be decoupled to the same ground plane as the
rest of the chip. A separate ground for DRVSS is not recommended.
The analog bypass pins (REFT and REFB) should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should be located close to
the pin.
The H1 to H8, HL, and RG traces should be designed to have
low inductance to minimize distortion of the signals. The com-
plementary signals, H1/H3/H5/H7 and H2/H4/H6/H8, should
be routed as close together and as symmetrically as possible to
minimize mutual inductance. Heavier PCB traces are recom-
mended because of the large transient current demand on H1
to H8 by the CCD. If possible, physically locating the AD9920A
closer to the CCD reduces the inductance on these lines. The
routing path should be as direct as possible from the AD9920A
to the CCD.
Note that it is recommended that all H1 to H8 outputs on the
AD9920A be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs should
have only the AD9920A H1, H3, H5, and H7 outputs connected
together to drive CCD H1, and only the AD9920A H2, H4, H6,
and H8 outputs connected together to drive CCD H2.
Similarly, a CCD with H1, H2, H3, and H4 inputs should have
the following:
H1 and H3 connected to CCD H1
H2 and H4 connected to CCD H2
H5 and H7 connected to CCD H3
H6 and H8 connected to CCD H4
TYPICAL 3 V SYSTEM
The AD9920A typical circuit connections for a 3 V system are
shown in Figure 110 and Figure 112. This application uses an
external 3.3 V supply, which is connected to the LDO input of
the AD9920A. The LDO provides 1.8 V to the AVDD, TCVDD,
and DVDD pins.
EXTERNAL CRYSTAL APPLICATION
The AD9920A contains an on-chip oscillator for driving an
external crystal. Figure 108 shows an example application using
a typical 27 MHz crystal. There is an internal feedback resistor
(typical value ≈ 7 MΩ). However, in the event that the internal
resistance is too high and prevents proper crystal operation, an
external resistor can be added in parallel. The value of this
external resistor is typically between 1 MΩ and 2 MΩ. For the
exact value of this resistor and other necessary external resistors
and capacitors, it is best to consult the crystal manufacturer.
Note that a 2× crystal is not recommended for use with the
CLO oscillator circuit. The crystal frequency should not exceed
40.5 MHz.
5pF TO 20pF
CLI
CLO
AD9920A
XTAL
~7M
USER DEFINED
~375
J5
K5
0
68
78
-10
8
Figure 108. Crystal Application Using CLI/CLO
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