參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/112頁(yè)
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 108 of 112
Table 63. V-Sequence (VSEQ) Registers (Default Values Are Undefined)
Address
Data
Bits
Default
Value
Update
Type
Name
Description
0x00
[0]
X
SCP
CLPOBPOL
CLPOB start polarity.
[1]
X
PBLKPOL
PBLK start polarity.
[5:2]
X
HOLD
1 = enable HOLD function for each VPAT group (A, B, C, D).
[6]
X
VSEQALT_EN
Special V-sequence alternation enable.
[9:7]
X
SPC_PAT_EN
1 = enable use of special vertical pattern insertion into VPATA sequence.
Bit 0: Use VPATB as the special pattern.
Bit 1: Use VPATC as the special pattern.
Bit 2: Use VPATD as the special pattern.
[13:10]
X
CONCAT_GRP
Combine multiple VPAT groups together in one sequence. Set register
equal to 0x01 to enable.
[15:14]
X
VREP_MODE
Defines V-alternation repetition mode.
00 = single-pattern alternation for all groups.
01 = two-pattern alternation for all groups.
10 = three-pattern alternation for Group A; Groups B/C/D follow pattern
{0, 1, 1, 0, 1, 1…}.
11 = four-pattern alternation for Group A; two-pattern for Groups B/C/D.
[19:16]
X
LASTREPLEN_EN
Enable a separate pattern length to be used during the last repetition of
the V-sequence. One bit for each group (A, B, C, and D); Group A is the LSB.
Set bit high to enable. Recommended value is enabled.
[21:20]
X
HBLK_MODE
Selection of HBLK modes.
00 = HBLK Mode 0 (normal six-toggle operation).
01 = HBLK Mode 1.
10 = test use only; do not access.
11 = test use only; do not access.
[23:22]
X
Test
Test use only. Set to 0.
[24]
X
SUBCK_MASK
1 = enable SUBCK masking feature.
0x01
[13:0]
X
SCP
HDLENE
HD line length for even lines.
0x02
[13:0]
X
SCP
HDLENO
HD line length for odd lines.
0x03
[23:0]
X
SCP
VSGPATSEL
Select which two toggle positions are used by each V-output
when they are configured as VSG pulses (in Miscellaneous Register 0x1C).
0 = use Toggle 1, Toggle 2.
1 = use Toggle 3, Toggle 4.
0x04
[12:0]
X
SCP
LASTREPLEN_A
Last repetition length for Group A. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENA register.
[25:13]
X
LASTREPLEN_B
Last repetition length for Group B. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENB register.
0x05
[12:0]
X
SCP
LASTREPLEN_C
Last repetition length for Group C. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENC register.
[25:13]
X
LASTREPLEN_D
Last repetition length for Group D. Must be enabled using LASTREPLEN_EN
register. Set equal to VLEND register.
0x06
[23:0]
X
SCP
VPOL
Starting polarities for each V-output signal.
0x07
[23:0]
X
SCP
GROUPSEL_0
Select to which group each V1 to V12 signal is assigned.
00 = Group A.
01 = Group B.
10 = Group C.
11 = Group D.
Bits[1:0]: V1.
Bits[3:2]: V2.
Bits[23:22]: V12.
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