參數(shù)資料
型號(hào)： AD9920ABBCZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 84/112頁(yè)
文件大小： 0K
描述： IC PROCESSOR CCD 12BIT 105CSPBGA
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 12
電壓 - 電源，模擬： 1.6 V ~ 2 V
電壓 - 電源，數(shù)字： 1.6 V ~ 2 V
封裝/外殼： 105-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 105-CSPBGA（8x8）
包裝： 帶卷 (TR)
AD9920A
Rev. B | Page 73 of 112
MANUAL SHUTTER OPERATION USING
ENHANCED SYNC MODES
The AD9920A also supports an external signal to control exposure,
using the SYNC input. Generally, the SYNC input is used as an
asynchronous reset signal during master mode operation. When
the enhanced SYNC mode is enabled, the SYNC input provides
additional control of the exposure operation.
Normal SYNC Mode (Mode 1)
By default, the SYNC input is used in master mode to synchronize
the internal counters of the AD9920A with external timing. The
horizontal, vertical, and field designator signals are reset by the
rising edge of the SYNC pulse. Figure 94 shows how this mode
operates, highlighting the behavior of the mode field designator.
Enhanced SYNC Modes (Mode 2 and Mode 3)
The enhanced SYNC modes can be used to accommodate unique
synchronization requirements during exposure operations. In
SYNC Mode 2, the V and VSG outputs are suspended and the
VD output is masked. The V-outputs are held at the dc value
established by the V-Sequence 0 start polarities. There is no SCP
operation, but the H-counter is still enabled. Finally, the AFE
sampling clocks, HD, H/RG, CLPOB, and HBLK, are operational
and use V-Sequence 0 behavior. See Figure 95 for more details.
To enable the enhanced SYNC modes, set the ENH_SYNC_EN
register (Address 0x13, Bit 3) to 1.
SYNC Mode 3 uses all the features of Mode 2, but the V-outputs
are continuous through the SYNC pulse interval. VD control
pulses are masked during the SYNC interval, and the HD pulse
can also be masked, if required (see Figure 96).
It is important to note that in both enhanced modes, the SYNC
pulse resets the counters at both the falling edge and the rising
edge of the SYNC pulse.
Register Update and Field Designator
When using SYNC Mode 2 or SYNC Mode 3, VD-updated
registers, such as PRIMARY_ACTION, are not updated during
the SYNC interval, and the SCP0 function is ignored and held
at 0 (see Figure 97).
When using either SYNC Mode 2 or SYNC Mode 3, both the
rising and falling edges increment the internal field designator;
therefore, the new register data takes effect and VTP information is
updated to new SEQ0 data. However, this does not occur if the
mode register is creating an output of one field. In that case, the
region, sequence, and group information does not change (see
Shutter Operation in SLR Mode
The following steps are shown in Figure 99.
1.
To turn on VSUB, write to the appropriate GP registers to
trigger VSUB and start the manual exposure (PRIMARY_
ACTION = 5). This change takes effect after the next VD.
SUBCK is suppressed during the exposure and readout
phases.
2.
To turn on MSHUT during the interval between the next
VD and SYNC, write to the appropriate GP register. When
MSHUT is in the on position, it has line and pixel control.
This change takes effect on the SYNC falling edge because
there is an internal VD.
3.
If the mode register is programmed to cycle through
multiple fields (5, 7, 3, 5, 7, 3, …, in this example), the
internal field designator increments. If the mode register
is not required to increment, set up the mode register such
that it outputs only one field. This prevents the mode
counter from incrementing during the SYNC interval.
4.
Write to the manual readout trigger to begin the manual
readout (PRIMARY_ACTION = 6). Write to the appropriate
GP registers to trigger MSHUT to toggle low at the end of
the exposure. This change takes effect on the SYNC rising
edge during readout. Because VD register update is disabled,
the trigger takes effect on the SYNC rising edge. The MSHUT
falling edge is aligned with the SYNC rising edge. Because
the MSHUT falling edge is aligned with VD, it may be
necessary to insert a dummy VD to delay the readout.
Because the internal exposure counter (the primary counter) is
not used during manual SYNC mode operation and the VD
register update is disabled, control is lost on the fine placement
of the GP signals for VSUB, MSHUT, and STROBE edges while
SYNC is low.
Serial Registers for Enhanced SYNC Modes
SYNC Mode 2 and SYNC Mode 3 are controlled using the
registers listed in Table 47. These registers are located at
Address 0x13, Bits[6:3].
Table 47. Registers for Enhanced SYNC Modes
Register
Length
(Bits)
Description
ENH_SYNC_EN
1
High active to enable masking
(default low)
SYNC_MASK_V
1
High active to enable masking
(default high)
SYNC_MASK_VD
1
High active to enable masking
(default high)
SYNC_MASK_HD
1
High active to enable masking
(default low)
相關(guān)PDF資料
PDF描述
AD9978BCPZRL IC PROCESSOR CCD 14BIT 40-LFCSP
ADADC71KD IC ADC 16BIT HIGH RES 32-CDIP
ADADC80-Z-12 IC ADC 12BIT INTEGRATED 32-CDIP
ADATE207BBPZ IC TIMING FORMATTER QUAD 256BGA
ADC0804LCN IC ADC 8-BIT 10KSPS 1LSB 20-DIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9920BBCZ 制造商:Analog Devices 功能描述:
AD9920BBCZRL 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9921BBCZ 制造商:Analog Devices 功能描述:
AD9921BBCZRL 制造商:Analog Devices 功能描述:
AD9923A 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processor with V-Driver and Precision Timing⑩ Generator
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*