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參數(shù)資料
| 型號： | AD9920ABBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 54/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD 12BIT 105CSPBGA |
| 標準包裝： | 2,000 |
| 位數(shù)： | 12 |
| 電壓 - 電源，模擬： | 1.6 V ~ 2 V |
| 電壓 - 電源，數(shù)字： | 1.6 V ~ 2 V |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應商設備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9920A
Rev. B | Page 46 of 112
VD
REGION 0
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION.
3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S).
XV1 TO XVx
HD
SCP1
SCP2
SEQ0
SEQ1
SCP3
SEQ2
SCP4
SEQ3
SCP5
SEQ4
SCP8
SEQ8
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
VSG
SGACTLINE1
SCP0
06
87
8-
0
56
Figure 57. Complete Field Divided into Regions
VD
XV1 TO XVx
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP1
SCP2
06
87
8-
0
57
Figure 58. Example of Sweep Region for High Speed Vertical Shift
Sweep Mode Operation
The AD9920A contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. An example of where this mode is needed is at the start of
the CCD readout operation. At the end of the image exposure
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the vertical outputs. Depending on
the vertical resolution of the CCD, up to 3000 clock cycles
might be needed to shift the charge out of each vertical CCD
line. This operation spans across multiple HD line lengths.
Normally, the AD9920A vertical timing must be contained
within one HD line length, but when sweep mode is enabled,
the HD boundaries are ignored until the region is finished. To
enable sweep mode within any region, program the appropriate
SWEEP register to high.
Figure 58 shows an example of the sweep mode operation. The
number of vertical pulses needed depends on the vertical reso-
lution of the CCD. The toggle positions for the XV1 to XV24
signals are generated using the V-pattern registers (see Table 14).
A single pulse is created using the polarity and toggle position
registers. The number of repetitions is then programmed to match
the number of vertical shifts required by the CCD. Repetitions
are programmed into the V-sequence registers using the VREP
registers (see Table 15). This produces a pulse train of the appro-
priate length. Normally, the pulse train is truncated at the end
of the HD line length, but when sweep mode is enabled for this
region, the HD boundaries are ignored.
In Figure 58, the sweep region occupies 23 HD lines. After the
sweep mode region is complete, normal sequence operation
resumes in the next region. When using sweep mode, be sure to
set the region boundaries (using the sequence change positions)
to the appropriate lines to prevent the sweep operation from
overlapping with the next V-sequence.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9920BBCZ | 制造商:Analog Devices 功能描述: |
| AD9920BBCZRL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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