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參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 69/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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Data Sheet
AD9520-5
Rev. A | Page 71 of 76
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9520
The AD9520 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9520, keep in mind the following
guidelines.
The AD9520 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
When determining a starting point, choosing a nominal charge
pump current in the middle of the allowable range allows the
designer to increase or decrease the charge pump current and,
thus, allows fine-tuning of the PLL loop bandwidth in either
direction.
Analog Devices, Inc., has an AD9520 configuration tool that can
determine the best PLL configuration, based on the user’s input
and output frequencies. It can also design the loop filter based
on user requirements.
In addition to the configuration tool, ADIsimCLK is a powerful
PLL modeling tool and a very accurate tool for determining the
optimal loop filter for a given application.
USING THE AD9520 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
AD9520 sampling clock. An ADC can be thought of as a sampling
mixer; and any noise, distortion, or time jitter on the clock is
combined with the desired signal at the analog-to-digital output.
Clock integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
Considering an ideal ADC of infinite resolution where the step
size and quantization error can be ignored, the available SNR
can be expressed, approximately, by the following equation:
π
=
J
At
f
SNR
2
1
log
20
(dB)
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 58 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
Figure 58. SNR and ENOB vs. Analog Input Frequency
For more information, see the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter;
and the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential LVPECL outputs of the AD9520 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or single-
ended, logic level termination) should be considered when
selecting the best clocking/converter solution.
fA (MHz)
S
NR
(
d
B)
E
NO
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
t
J = 100f
s
t
J = 200f
s
t
J = 400f
s
t
J = 1p
s
t
J = 2p
s
t
J = 10p
s
SNR = 20log
1
2πfAtJ
07239-
044
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