- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16544 > AD9520-5/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9520-5 PDF資料下載
參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
Data Sheet
AD9520-5
Rev. A | Page 43 of 76
LVPECL Output Drivers
The LVPECL differential voltage (VOD) is selectable (from
~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to
Register 0x0FB). The LVPECL outputs have dedicated pins for
power supply (VS_DRV), allowing a separate power supply to
be used. VS_DRV can be set to either 2.5 V or 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have two power-down
modes: total power-down and safe power-down.
Figure 42. LVPECL Output Simplified Equivalent Circuit
In total power-down mode, all output drivers are shut off
simultaneously. This mode must not be used if there is an
external voltage bias network (such as Thevenin equivalent
termination) on the output pins that causes a dc voltage to
appear at the powered down outputs. However, total power-
down mode is allowed when the LVPECL drivers are terminated
using only pull-down resistors. The total power-down mode is
activated by setting Register 0x230[1].
The primary power-down mode is the safe power-down mode.
This mode continues to protect the output devices while
powered down. There are three ways to activate safe power-
down mode: individually set the power-down bit for each
driver, power down an individual output channel (all of the
drivers associated with that channel are powered down
automatically), and activate sleep mode.
CMOS Output Drivers
The user can also individually configure each LVPECL output as a
pair of CMOS outputs, which provides up to 24 CMOS outputs.
When an output is configured as CMOS, CMOS Output A and
CMOS Output B are automatically turned on. For any given
differential pair, either CMOS Output A or CMOS Output B can
be turned on or off independently.
The user can also select the relative polarity of the CMOS outputs
for any combination of inverting and noninverting (refer to
Register 0x0F0 to Register 0x0FB).
Figure 43. CMOS Equivalent Output Circuit
Each CMOS output can be powered down, as needed, to save
power. The CMOS output power-down is individually controlled
by the enable CMOS output bits, Bits[6:5] in Register 0x0F0 to
Register 0x0FB. The CMOS driver is in tristate when it is
powered down.
Note that activating a CMOS driver in the same output channel
group as the LVPECL drivers may cause the LVPECL driver
performance to degrade. In applications where jitter
performance is critical, the user should test the desired
configuration using an evaluation board, and special steps may
need to be taken to ensure the desired performance.
RESET MODES
The AD9520 has a power-on reset (POR) and several other
ways to apply a reset condition to the chip.
Power-On Reset
During chip power-up, a power-on reset pulse is issued when
VS reaches ~2.6 V (<2.8 V) and restores the chip either to the
setting that is stored in the EEPROM (with the EEPROM pin = 1b)
or to the on-chip setting (with the EEPROM pin = 0b). At power-
on, the AD9520 also executes a SYNC operation approximately
50 ms after the supply reaches ~2.4 V, which brings the outputs
into phase alignment according to the default settings.
It takes ~70 ms for the outputs to begin toggling after the
power-on reset pulse signal is internally generated.
Hardware Reset via the RESET Pin
RESET, a hard reset (an asynchronous hard reset is executed by
briefly pulling RESET low), restores the chip either to the setting
stored in the EEPROM (the EEPROM pin = 1b) or to the on-chip
setting (the EEPROM pin = 0b). A hard reset also executes
a SYNC operation, bringing the outputs into phase alignment
according to the default settings. When the EEPROM is inactive
(the EEPROM pin = 0b), it takes ~2 s for the outputs to begin
toggling after RESET is issued. When the EEPROM is active
(the EEPROM pin = 1b), it takes ~20 ms for the outputs to toggle
after RESET is brought high.
R2
200
R1
200
SW1B
SW1A
SW2
QN2
QN1
N2
N1
OUT
4.4mA
07239-
058
OUT1/
OUT1
VS_DRV
07239-
035
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACM06DRYN | CONN EDGECARD 12POS DIP .156 SLD |
| SPD42R-823M | INDUCTOR PWR SHIELDED 82UH SMD |
| EBA30DTKS | CONN EDGECARD 60POS DIP .125 SLD |
| CDK2000-LCO | KIT EVAL PROTOTYPING CS2300-CP |
| ECE-T2GP821FA | CAP ALUM 820UF 400V 20% SNAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521KH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。