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參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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Data Sheet
AD9520-5
Rev. A | Page 3 of 76
REVISION HISTORY
8/13—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
General Description Section............................................................1
Changes to Table 2 ............................................................................4
Changes to Input Frequency Parameter; Change to Input
Sensitivity, Differential Parameter Test Conditions/Comments,
Table 3.................................................................................................7
Change to Output Differential Voltage, VOD Parameter Test
Conditions/Comments; Added Source Current and Sink
Current Parameters, Table 4 ............................................................7
Reordered Figure 2 to Figure 4........................................................9
Change to Reset Timing, Pulse Width Low Parameter, Table 12...14
Change to Junction Temperature, Table 16; Reformatted
Table 16........................................................................................................16
Added NC Note to Figure 5; Change to Pin 4 and Pin 22
Description, Table 18 ......................................................................17
Reordered Figure 21 and Figure 22 ..............................................22
Added Figure 25, Renumbered Sequentially...............................23
Change to Configuration of the PLL Section and Changes
to Charge Pump (CP) Section .......................................................30
Change to PLL Reference Inputs Section; Changes to
Reference Switchover Section........................................................31
Change to Prescaler Section and A and B Counters Section ....32
Changes to Table 25 ........................................................................33
Change to Clock Frequency Division Section; Changes to
VCO Divider Section; Added Channel Divider Maximum
Frequency Section...........................................................................39
Reformatted Table 30 to Table 33..................................................40
Change to Phase Offset or Coarse Time Delay Section.............41
Change to LVPECL Output Drivers Section; Changes to CMOS
Output Drivers Section and Power-On Reset Section ...............43
Changes to Soft Reset via the Serial Port Section and Soft
Reset to Settings in EEPROM when EEPROM Pin = 0b
via the Serial Port Section ..............................................................44
Change to Pin Descriptions Section and SPI Mode Operation
Section ..............................................................................................48
Changes to SPI Instruction Word (16 Bits) Section ...................49
Changes to EEPROM Operations Section, Writing to the
EEPROM Section, and Reading from the EEPROM Section ...52
Changes to Register Section Definition Group Section;
Added Operational Codes Section Heading ...............................53
Changes to Table 44 ........................................................................55
Added Unused Bits to Register Map Descriptions Section;
Changes to Address 0x000, Bit 5, and Added Address 0x003,
Table 45; Changes to Address 0x000, Bit 5, and Added
Address 0x003, Table 46.................................................................58
Changes to Address 0x017, Bits[7:2], Table 48............................60
Changes to Address 0x018, Bit 4, Table 48 ..................................61
Changes to Address 0x01A, Bits[5:0], Setting 101010,
Table 48.............................................................................................62
Changes to Address 0x01B, Bits[4:0], Table 48 ...........................63
Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,
Table 50.............................................................................................66
Changes to Address 0x197, Bit 5, Table 50 ..................................67
Changes to Address 0x19A, Bit 5, Table 50 .................................68
Changes to Table 54 ........................................................................69
Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,
Table 55.............................................................................................70
Change to Frequency Planning Using the AD9520 Section .....71
Added LVPECL Y-Termination and Far-End Thevenin
Termination Headings; Changes to CMOS Clock Distribution
Section ..............................................................................................72
10/08—Revision 0: Initial Version
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