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參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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Data Sheet
AD9520-5
Rev. A | Page 33 of 76
Table 25. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
fREF (MHz)
R
P
A
B
N
fVCO (MHz)
Mode
Description
10
1
1
10
FD
P = 1, B = 1 (A and B counters are bypassed).
10
1
2
1
2
20
FD
P = 2, B = 1 (A and B counters are bypassed).
10
1
3
30
FD
A counter is bypassed.
10
1
4
40
FD
A counter is bypassed.
10
1
5
50
FD
A counter is bypassed.
10
1
2
3
6
60
FD
A counter is bypassed.
10
1
2
0
3
6
60
DM
10
1
2
1
3
7
70
DM
Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.
If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz
to 300 MHz, use P = 1 and N = 7 or 11, respectively.
10
1
2
3
8
80
DM
10
1
2
1
4
9
90
DM
10
1
8
6
18
150
1500
DM
10
1
8
7
18
151
1510
DM
10
1
16
7
9
151
1510
DM
10
32
6
47
1510
DM
10
1
8
0
25
200
2000
DM
10
1
16
0
15
240
2400
DM
10
32
0
75
2400
DM
1 X = don’t care.
R, A, and B Counters—SYNC Pin Reset
The R, A, and B counters can be reset simultaneously through the
SYNC pin. This function is controlled by Register 0x019[7:6]
(see Table 48). The SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 2 and Table 48.
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock detect
window bit (Register 0x018[4]), the antibacklash pulse width bit
(Register 0x017[1:0], see Table 2), and the lock detect counter
(Register 0x018[6:5]). The lock and unlock detection values
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference that is less than
the lock detect threshold. The lock detect circuit continues to
indicate a lock until a time difference that is greater than the
unlock threshold occurs on a single subsequent cycle. For the
lock detect to work properly, the period of the PFD frequency
must be greater than the unlock threshold. The number of
consecutive PFD cycles required for lock is programmable
(Register 0x018[6:5]).
Note that, in certain low (<500 Hz) loop bandwidth, high phase
margin cases, the DLD may chatter during acquisition, which can
cause the AD9520 to automatically enter and exit holdover. To
avoid this problem, it is recommended that the user provide for
a capacitor to ground on the LD pin such that current source
digital lock detect (CSDLD) mode can be used.
Analog Lock Detect (ALD)
The AD9520 provides an ALD function that can be selected for
use at the LD pin. There are two operating modes for ALD:
N-channel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low going pulses. Lock is indicated
by the minimum duty cycle of the low going pulses.
P-channel open-drain lock detect. This signal requires a
pull-down resistor to GND. The output is normally low with
short, high going pulses. Lock is indicated by the minimum
duty cycle of the high going pulses.
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