- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16544 > AD9520-5/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9520-5 PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當(dāng)前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD9520-5
Data Sheet
Rev. A | Page 62 of 76
Reg.
Addr.
(Hex)
Bits Name
Description
[5:0] LD pin control
Selects the signal that is connected to the LD pin.
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock; low = unlock, default).
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
1
HIZ
Tristate (high-Z) LD pin.
0
1
0
CUR
Current source lock detect (110 A when DLD is true).
0
X
LVL
Ground (dc). Used for all settings of these bits not otherwise specified in this table.
The selections that follow are also used for REFMON and STATUS pin control.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
1
0
1
LVL
Status of REF1 frequency; active high.
1
0
1
0
LVL
Status of REF2 frequency; active high.
1
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK).
1
0
1
0
1
LVL
Status of CLK frequency; active high.
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
DLD; active high.
1
0
1
0
LVL
Holdover active; active high.
1
0
1
LVL
N/A. Do not use.
1
0
LVL
VS (PLL power supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency; active low.
1
0
LVL
Status of REF2 frequency; active low.
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO)
1
0
1
LVL
Status of CLK frequency; active low.
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD; active low.
1
0
LVL
Holdover active; active low.
1
LVL
N/A. Do not use.
0x01B 7
Enable CLK
frequency monitor
Enables or disables the external CLK frequency monitor.
0: disables the external CLK frequency monitor (default).
1: enables the external CLK frequency monitor.
6
Enable REF2
(REFIN) frequency
monitor
Enables or disables the REF2 frequency monitor.
0: disables the REF2 frequency monitor (default).
1: enables the REF2 frequency monitor.
5
Enable REF1
(REFIN) frequency
monitor
REF1 (REFIN) frequency monitor enabled; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by
differential reference mode).
0: disables the REF1 (REFIN) frequency monitor (default).
1: enables the REF1 (REFIN) frequency monitor.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACM06DRYN | CONN EDGECARD 12POS DIP .156 SLD |
| SPD42R-823M | INDUCTOR PWR SHIELDED 82UH SMD |
| EBA30DTKS | CONN EDGECARD 60POS DIP .125 SLD |
| CDK2000-LCO | KIT EVAL PROTOTYPING CS2300-CP |
| ECE-T2GP821FA | CAP ALUM 820UF 400V 20% SNAP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521KH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。