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參數(shù)資料
| 型號(hào)： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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AD9520-5
Data Sheet
Rev. A | Page 36 of 76
The following registers affect the automatic/internal holdover
function:
Register 0x018[6:5]—lock detect counter. This changes
how many consecutive PFD cycles with edges inside the
lock detect window are required for the DLD indicator to
indicate lock. This impacts the time required before the LD
pin can begin to charge as well as the delay from the end of
a holdover event until the holdover function can be
reengaged.
Register 0x018[3]—disable digital lock detect. This bit must
be set to 0b to enable the DLD circuit. Automatic/internal
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0]—lock detect pin control. Set these bits
to 000100b to program the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x01D[3]—LD pin comparator enable. 1b = enable;
0b = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1]—external holdover control.
Register 0x01D[0]—holdover enable. If holdover is
disabled, both external and automatic/internal holdover
are disabled.
In the following example, automatic holdover is configured with
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
The following registers are set (in addition to the normal PLL
registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; digital lock detect window = high
range.
Register 0x018[3] = 1b; disable DLD normal operation.
Register 0x01A[5:0] = 000100b; program LD pin control to
current source lock detect mode.
Register 0x01C[4] = 1b; enable automatic switchover.
Register 0x01C[3] = 0b; prefer REF1.
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[1] = 0b; disable external holdover mode and
use automatic/internal holdover mode.
Register 0x01D[0] = 1b; enable holdover.
Frequency Status Monitors
The AD9520 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the external CLK input have fallen
below a threshold frequency. Figure 36 shows the location of the
frequency status monitors in the PLL.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 14). The reference frequency
monitor thresholds are set in Register 0x01A[6].
Figure 36. Reference and CLK Frequency Status Monitors
PROGRAMMABLE
N DELAY
CLK
REF1
REF2
BUF
STATUS
R
DI
V
IDE
R
CL
O
CK
DO
UBL
E
R
CLK FREQUENCY STATUS
P
RO
G
RAM
M
ABL
E
R
DE
L
AY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NCE
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
ZERO DELAY BLOCK
FROM CHANNEL
DIVIDER 0
VS_DRV
REFIN
OPTIONAL
REFIN
07239-
070
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