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參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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Data Sheet
AD9520-5
Rev. A | Page 19 of 76
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
47
O
LVPECL or
CMOS
OUT3 (OUT3B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
48
O
LVPECL or
CMOS
OUT3 (OUT3A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
50
O
LVPECL or
CMOS
OUT2 (OUT2B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
51
O
LVPECL or
CMOS
OUT2 (OUT2A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output o r as a single-ended CMOS output.
52
O
LVPECL or
CMOS
OUT1 (OUT1B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
53
O
LVPECL or
CMOS
OUT1 (OUT1A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
55
O
LVPECL or
CMOS
OUT0 (OUT0B)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
56
O
LVPECL or
CMOS
OUT0 (OUT0A)
Clock Output. This pin can be configured as one side of a differential LVPECL
output or as a single-ended CMOS output.
58
O
Current set
resistor
RSET
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin
to GND.
62
O
Current set
resistor
CPRSET
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND.
This resistor can be omitted if the PLL is not used.
63
I
Reference
input
REFIN (REF2)
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF2. This pin can be left unconnected when
the PLL is not used.
64
I
Reference
input
REFIN (REF1)
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF1.This pin can be left unconnected when
the PLL is not used.
EPAD
GND
The exposed die pad must be connected to GND.
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