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參數(shù)資料
| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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AD9520-5
Data Sheet
Rev. A | Page 26 of 76
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9520 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 44 to Table 55). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. After the desired
configuration is programmed, the user can store these values in the
on-board EEPROM to allow the part to power up in the desired
configuration without user intervention.
Mode 1—Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is <1600 MHz, a configuration that bypasses the
VCO divider can be used. This is the only difference from Mode 2.
Bypassing the VCO divider limits the frequency of the clock
source to <1600 MHz (due to the maximum input frequency
allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
<1600 MHz, use the register settings shown in Table 19.
Table 19. Settings for Clock Distribution < 1600 MHz
Register
Description
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E1[0] = 1b
Bypass the VCO divider as the source for
the distribution section
0x1E1[1] = 0b
Select CLK as the source
When the internal PLL is used with an external VCO < 1600 MHz,
the PLL must be turned on.
Table 20. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
Description
0x1E1[0] = 1b
Bypass the VCO divider as the source for
the distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on) along with
other appropriate PLL settings in Register
0x010 to Register 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between the CP pin and the tuning pin of
the VCO/ VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 21. Setting the PFD Polarity
Register
Description
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
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