AD9520-5
Data Sheet
Rev. A | Page 42 of 76
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0]. Both setting
and resetting of the soft SYNC bit require an update all registers
(Register 0x232[0] = 1b) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state of
each output when the SYNC operation is happening and the state
and relative phase of the outputs when they begin clocking again
upon completion of the SYNC operation. Between outputs and
after synchronization, this allows for the setting of phase offsets.
The
AD9520 differential LVPECL outputs are four groups of
three, sharing a channel divider per triplet. In the case of CMOS,
each LVPECL differential pair can be configured as two single-
ended CMOS outputs. The synchronization conditions apply to all
of the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the ignore SYNC bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
Figure 40. SYNC Timing Pipeline Delay When the VCO Divider Is Used
Figure 41. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used
1
2
3
4
5
6
7
8
9
10
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
07239-
073
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
07239-
074