參數(shù)資料
型號(hào)： AD9520-5/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/76頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9520-5
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9520-5
已供物品： 板
AD9520-5
Data Sheet
Rev. A | Page 12 of 76
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 9.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
Channel Divider = 2; Duty-Cycle Correction = Off
230
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
215
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL;
uses rising edge of clock signal
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
326
fs rms
Calculated from SNR of ADC method
(broadband jitter)
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Channel Divider = 8; Duty-Cycle Correction = Off
362
fs rms
Calculated from SNR of ADC method
(broadband jitter)
SERIAL CONTROL PORT—SPI MODE
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
A
Input Logic 0 Current
110
A
The minus sign indicates that current is
flowing out of the AD9520, which is due to
the internal pull-up resistor
Input Capacitance
2
pF
SCLK (INPUT) IN SPI MODE
SCLK has an internal 30 kΩ pull-down resistor
in SPI mode, but not in I2C mode
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
A
Input Logic 0 Current
1
A
Input Capacitance
2
pF
SDIO (INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
1
A
Input Logic 0 Current
1
A
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
4
ns
SCLK to SDIO Hold, tDH
0
ns
SCLK to Valid SDIO and SDO, tDV
11
ns
CS to SCLK Setup and Hold, tS, tC
2
ns
CS Minimum Pulse Width High, tPWH
3
ns
相關(guān)PDF資料
PDF描述
ACM06DRYN CONN EDGECARD 12POS DIP .156 SLD
SPD42R-823M INDUCTOR PWR SHIELDED 82UH SMD
EBA30DTKS CONN EDGECARD 60POS DIP .125 SLD
CDK2000-LCO KIT EVAL PROTOTYPING CS2300-CP
ECE-T2GP821FA CAP ALUM 820UF 400V 20% SNAP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9521JH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521KH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521TE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*