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| 型號： | AD9520-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9520-5 |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 已用 IC / 零件： | AD9520-5 |
| 已供物品： | 板 |
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AD9520-5
Data Sheet
Rev. A | Page 38 of 76
Figure 38. Simplified Diagram of the Two Clock Distribution Operation Modes
CLOCK DISTRIBUTION
A clock channel consists of three LVPECL clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVPECL or CMOS at the pins.
The AD9520 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer from
1 to 32.
The AD9520 features a VCO divider that divides the CLK input by
1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz.
The other is to allow the AD9520 to generate even lower
frequencies than would be possible with only a simple post divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
Operation Modes
There are two clock distribution operating modes, as shown in
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 26 shows how the operation modes are selected. Bit 0 of
Register 0x1E1 selects the channel divider source.
Table 26. Operation Modes
Mode
Register 0x1E1[0]
VCO Divider
2
0
Used
1
Not used
CLK Direct-to-LVPECL Outputs
It is possible to connect the CLK directly to the LVPECL
outputs. However, the LVPECL outputs may not be able to meet
To connect the LVPECL outputs directly to the CLK input, the
user must select the VCO divider as the source to the distribution
section, even if no channel uses it.
Table 27. Routing VCO Divider Input Directly to the Outputs
Register Setting
Selection
0x1E1[0] = 0b
VCO divider selected
0x192[1] = 1b
Direct-to-output OUT0, OUT1, OUT2
0x195[1] = 1b
Direct-to-output OUT3, OUT4, OUT5
0x198[1] = 1b
Direct-to-output OUT6, OUT7, OUT8
0x19B[1] = 1b
Direct-to-output OUT9, OUT10, OUT11
MODE 1 (CLOCK DISTRIBUTION MODE)
DISTRIBUTION
CLOCK
MODE 2 (HF CLOCK DISTRIBUTION MODE)
CLK
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
CLK
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLOCK
DISTRI-
BUTION
PLL
DISTRIBUTION
CLOCK
07239-
054
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