參數(shù)資料
型號: AD9520-5/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 16/76頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9520-5
設(shè)計資源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
AD9520 Eval Brd Schematic
AD9520 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
已用 IC / 零件: AD9520-5
已供物品:
Data Sheet
AD9520-5
Rev. A | Page 23 of 76
Figure 22. Additive (Residual) Phase Noise, CLK-to-CMOS at 50 MHz,
Divide-by-20
Figure 23. Additive (Residual) Phase Noise, CLK-to-CMOS at
250 MHz, Divide-by-4
Figure 24. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
Figure 25. Telcordia GR-253 Jitter Tolerance Plot
–110
–120
–130
–140
–150
–170
–160
10
1k
100
100M
1M
10M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
07239-
131
–100
–110
–120
–130
–140
–150
–160
10
1k
100
100M
1M
10M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
07239-
132
1k
100M
1M
10M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
–120
–160
–150
–140
–130
07239-
135
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
JITTER FREQUENCY (kHz)
OC-48 OBJECTIVE MASK
AD9520
fOBJ
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
IN
P
U
T
J
ITTE
R
A
M
P
LITU
D
E
(
U
Ip-
p)
07239-
134
相關(guān)PDF資料
PDF描述
ACM06DRYN CONN EDGECARD 12POS DIP .156 SLD
SPD42R-823M INDUCTOR PWR SHIELDED 82UH SMD
EBA30DTKS CONN EDGECARD 60POS DIP .125 SLD
CDK2000-LCO KIT EVAL PROTOTYPING CS2300-CP
ECE-T2GP821FA CAP ALUM 820UF 400V 20% SNAP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9521JH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521KH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521SH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier
AD9521TE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier