- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F016XS (Intel Corp.) 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲器) PDF資料下載
參數(shù)資料
| 型號： | 28F016XS |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲器) |
| 中文描述： | 16兆位同步閃存（1,600位同步閃速存儲器） |
| 文件頁數(shù)： | 8/54頁 |
| 文件大?。?/td> | 830K |
| 代理商： | 28F016XS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
28F016XS FLASH MEMORY
E
8
address inputs. During read operations, addresses
are latched and accesses are initiated on a rising
CLK edge in conjunction with ADV# low. Both CLK
and ADV# are ignored by the 28F016XS during
command/data write sequences.
The
technology, providing V
operation at both 3.3V
and 5.0V and program and erase capability at
V
= 12.0V or 5.0V. Operating at V
= 3.3V, the
28F016XS consumes less than one half the power
consumption at 5.0V V
, while 5.0V V
CC
provides
highest read performance capability. V
operation
at 5.0V eliminates the need for a separate 12.0V
converter, while the V
= 12.0V option maximizes
program/erase performance. In addition to the
flexible program and erase voltages, the dedicated
V
PP
gives complete code protection with V
PP
≤
V
PPLK
.
28F016XS
incorporates
SmartVoltage
A 3/5# input pin configures the device’s internal
circuitry for optimal 3.3V or 5.0V read/program
operation.
A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows program and
block erase operations to be executed using a Two-
Write command sequence to the CUI in the same
way as the 28F008SA 8-Mbit FlashFile memory.
Software locking of memory blocks is an added
feature of the 28F016XS as compared to the
28F008SA. The 28F016XS provides selectable
block locking to protect code or data such as direct-
executable operating systems or application code.
Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In
addition, the 28F016XS has a master Write Protect
pin (WP#) which prevents any modifications to
memory blocks whose lock-bits are set.
Writing of memory data is performed in either byte
or word increments, typically within 6 μs at 12.0V
V
, which is a 33% improvement over the
28F008SA. A block erase operation erases one of
the 16 blocks in typically 1.2 sec, independent of
the other blocks.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling
algorithms and graceful block retirement. These
techniques have already been employed in many
flash file systems and hard disk drive designs.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later in this datasheet) and a
RY/BY# output pin provide information on the
progress of the requested operation.
The following Status Registers are used to provide
device and WSM operation information to the user:
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016XS from a 28F008SA-
based design.
A Global Status Register (GSR) which also
informs the system of overall Write State
Machine (WSM) status.
16 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
The GSR and BSR memory maps for Byte-Wide
and Word-Wide modes are shown in Figures 5
and 6.
The 28F016XS incorporates an open drain RY/BY#
output pin. This feature allows the user to OR-tie
many RY/BY# pins together in a multiple memory
configuration such as a Resident Flash Array.
The 28F016XS also incorporates a dual chip-
enable function with two input pins, CE
# and CE
#.
These pins have exactly the same functionality as
the regular chip-enable pin, CE#, on the 28F008SA.
For minimum chip designs, CE
# may be tied to
ground and system logic may use CE
# as the chip
enable input. The 28F016XS uses the logical
combination of these two signals to enable or
disable the entire chip. Both CE
# and CE
# must
be active low to enable the device. If either one
becomes inactive, the chip will be disabled. This
feature, along with the open drain RY/BY# pin,
allows the system designer to reduce the number of
control pins used in a large array of 16-Mbit
devices.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F020 | 5 V Bulk Erase Flash Memory(5V 整體擦寫閃速存儲器) |
| 28F128J3A | 3 Volt Intel StrataFlash Memory(3 V 128M位Strata閃速存儲器) |
| 28F320J3A | 3 Volt Intel StrataFlash Memory(3 V 32M位英特爾StrataFlash存儲器) |
| 28F640J3A | 3 Volt Intel StrataFlash Memory(3 V 64M位英特爾StrataFlash存儲器) |
| 28F128 | 3 Volt Intel StrataFlash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F0181-1SR-10 | 功能描述:電磁干擾濾波珠子、扼流圈和陣列 115ohms 100MHz 10A Broad Band Frequency RoHS:否 制造商:AVX 阻抗: 最大直流電流:35 mA 最大直流電阻: 容差: 端接類型:SMD/SMT 電壓額定值:25 V 工作溫度范圍:- 25 C to + 85 C 封裝 / 箱體:0603 (1608 metric) |
| 28F020 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| 28F020-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F020G12 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F020N12 | 制造商: 功能描述: 制造商:undefined 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。