參數(shù)資料
型號: 28F016XS
廠商: Intel Corp.
英文描述: 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲器)
中文描述: 16兆位同步閃存(1,600位同步閃速存儲器)
文件頁數(shù): 12/54頁
文件大?。?/td> 830K
代理商: 28F016XS
28F016XS FLASH MEMORY
E
12
2.1
Lead Descriptions
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when device is
in x8 mode. This address is latched in x8 data programs and ignored in x16
mode (i.e., the A
0
input buffer is turned off when BYTE# is high).
A
1
INPUT
BANK-SELECT ADDRESS:
Selects an even or odd bank in a selected block.
A 128-Kbyte block is subdivided into an even and odd bank. A
1
= 0 selects the
even bank and A
1
= 1 selects the odd bank, in both byte-wide mode and word-
wide mode device configurations.
A
2
–A
16
INPUT
WORD-SELECT ADDRESSES:
Select a word within one 128-Kbyte block.
Address A
1
and A
7
–16
select 1 of 2048 rows, and A
2–6
select 16 of 512
columns. These addresses are latched during both data reads and programs.
A
17
–A
20
INPUT
BLOCK-SELECT ADDRESSES:
Select 1 of 16 erase blocks. These
addresses are latched during data programs, erase and lock-block operations.
DQ
0
–DQ
7
INPUT/
OUTPUT
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write cycles.
Outputs array, identifier or status data in the appropriate read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ
8
–DQ
15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS:
Inputs data during x16 data program operations.
Outputs array or identifier data in the appropriate read mode; not used for
Status Register reads. Outputs floated when the chip is de-selected, the
outputs are disabled (OE# = V
IH
) or BYTE# is driven active.
CE
0
#, CE
1
#
INPUT
CHIP ENABLE INPUTS:
Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE
0
# or CE
1
# high, the device is
de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE
0
# and
CE
1
# must be low to select the device.
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CE
0
# or CE
1
#. The first rising edge of CE
0
# or
CE
1
# disables the device.
RP#
INPUT
RESET/POWER-DOWN:
RP# low places the device in a deep power-down
state. All circuits that consume static power, even those circuits enabled in
standby mode, are turned off. When returning from deep power-down, a
recovery time of t
PHCH
is required to allow these circuits to power-up.
When RP# goes low, the current WSM operation is terminated, and the device
is reset. All Status Registers return to ready, clearing all status flags. Exit from
deep power-down places the device in read array mode.
OE#
INPUT
OUTPUT ENABLE:
Drives device data through the output buffers when low.
The outputs float to tri-state off when OE# is high. CEx# overrides OE#, and
OE# overrides WE#.
WE#
INPUT
WRITE ENABLE:
Controls
access to the CUI, Data Register and Address
Latch. WE# is active low, and latches both address and data (command or
array) on its rising edge.
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