參數(shù)資料
型號(hào)： 28F016XS
廠商： Intel Corp.
英文描述： 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲(chǔ)器)
中文描述： 16兆位同步閃存（1,600位同步閃速存儲(chǔ)器）
文件頁數(shù)： 43/54頁
文件大?。?/td> 830K
代理商： 28F016XS
E
28F016XS FLASH MEMORY
43
V
V
DEEP
POWER-DOWN
IH
IL
ADDRESSES (A)
tAVAV
t
WHAX
IN
A
READ EXTENDED
STATUS REGISTER DATA
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
V
VIH
IL
ADDRESSES (A)
tAVAV
AVWH
t
t
WHAX
IN
A
READ COMPATIBLE
STATUS REGISTER DATA
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
AVWH
t
CLK
NOTE 6
ADV#
NOTE 6
WE# (W)
OE# (G)
RP# (P)
V
PP
CEx # (E)
(V)
V
V
IH
IL
V
V
IH
IL
tWHEH
ELWL
t
t
WHDX
WHWL
t
V
V
IH
IL
t
WLWH
t
DVWH
V
IH
IL
V
VIH
VIL
PHWL
t
HIGH Z
IN
D
DIN
t
t
QVVL2
DIN
IL
V
PPH2
V
PPH1
V
t
VPWH2
DATA (D/Q)
WHQV1,2
V
V
RY/BY# (R)
tWHRL
t
WHCH
OH
OL
D
IN
NOTE 4
DOUT
t
RHPL
t
GHWL
NOTE 5
PPLK
V
NOTE 7
NOTE 8
t
VPWH1
t
QVVL1
0532_14
NOTES:
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/erase operations.
4. CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
5. RP# low transition is only to show t
RHPL
; not valid for above read and program cycles.
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.
7. V
PP
voltage during data program/erase operations valid at both 12.0V and 5.0V.
8. V
PP
voltage equal to or below V
PPLK
provides complete flash memory array protection.
Figure 15. AC Waveforms for WE#
—Command Write Operations,
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read
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