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參數(shù)資料
| 型號： | 28F016XS |
| 廠商： | Intel Corp. |
| 英文描述： | 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲器) |
| 中文描述： | 16兆位同步閃存（1,600位同步閃速存儲器） |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 830K |
| 代理商： | 28F016XS |
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E
4.2
28F016XS FLASH MEMORY
17
Bus Operations for Byte-Wide Mode (BYTE# = V
IL
)
Mode
Notes
RP#
CE
0
–1
#
OE#
WE#
ADV#
CLK
A
0
DQ
0–7
RY/BY#
Latch Read
Address
1,9,10
V
IH
V
IL
X
V
IH
V
IL
↑
X
X
X
Inhibit
Latching
Read Address
1,9
V
IH
V
IL
X
V
IH
V
IH
↑
X
X
X
Read
1,2,7,9
V
IH
V
IL
V
IL
V
IH
X
↑
X
D
OUT
X
Output
Disable
1,6,7,9
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
X
Standby
1,6,7,9
V
IH
V
IH
X
X
X
X
X
High Z
X
Deep
Power-Down
1,3
V
IL
X
X
X
X
X
X
High Z
V
OH
Manufacturer
ID
1,4,9
V
IH
V
IL
V
IL
V
IH
X
↑
V
IL
89H
V
OH
Device ID
1,4,8,9
V
IH
V
IL
V
IL
V
IH
X
↑
V
IH
A8H
V
OH
Write
1,5,6,9
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
X
NOTES:
1.
X can be V
or V
for address or control pins except for RY/BY#, which is either V
OL
or V
OH
, or High Z or D
OUT
for data
pins depending on whether or not OE# is active.
RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode,
RY/BY# will be at V
OH
if it is tied to V
CC
through a resistor. RY/BY# at V
OH
is independent of OE# while a WSM operation
is in progress.
RP# at GND ± 0.2V ensures the lowest deep power-down current.
A
and A
at V
provide device manufacturer codes in x8 and x16 modes respectively. A
0
and A
1
at V
IH
provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
Commands for erase, data program, or lock-block operations can only be completed successfully when V
PP
= V
PPH1
or
V
PP
= V
PPH2
.
While the WSM is running, RY/BY# stays at V
OL
until all operations are complete. RY/BY# goes to V
OH
when the WSM is
not busy or in erase suspend mode.
RY/BY# may be at V
OL
while the WSM is busy performing various operations (for example, a Status Register read during a
program operation).
The 28F016XS shares an identical device identifier with the 28F016XD.
CE
0
–1
# at V
IL
is defined as both CE
0
# and CE
1
# low, and CE
0–1
# at V
IH
is defined as either CE
0
# or CE
1
# high.
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A
= 0 selects the even bank and
A
1
= 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
2.
3.
4.
5.
6.
7.
8.
9.
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