參數(shù)資料
型號: 28F016XS
廠商: Intel Corp.
英文描述: 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲(chǔ)器)
中文描述: 16兆位同步閃存(1,600位同步閃速存儲(chǔ)器)
文件頁數(shù): 47/54頁
文件大?。?/td> 830K
代理商: 28F016XS
E
28F016XS FLASH MEMORY
47
CLK
NOTE 6
V
V
POWDEEP
IH
IL
ADDRESSES (A)
tAVAV
t
EHAX
IN
A
STAREAD EXTENDED
WRITE DATA-WRITE OR
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOR ERASE DELAY
V
IL
ADDRESSEVIH
t
AVAV
AVEH
t
tEHAX
IN
A
STREAD COMPATIBLE
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
AVEH
t
WE# (W)
OE# (G)
RP# (P)
VPP
CEx#(E)
(V)
V
V
IH
IL
V
V
IH
IL
tEHWH
WLEL
t
t
EHDX
EHEL
t
V
V
IH
IL
t
ELEH
t
DVEH
VIH
IL
V
VIH
VIL
PHEL
t
HIGH Z
IN
D
DIN
t
tQVVL2
DIN
IL
V
PPH1
V
PPH2
V
tVPEH2
DATA (D/Q)
EHQV1,2
V
V
RY/BY# (R)
tEHRL
tEHCH
OH
OL
D
IN
NOTE 4
D
OUT
t
RHPL
tGHEL
NOTE 5
PPLK
V
ADV#
NOTE 6
NOTE 7
NOTE 8
tVPEH1
t
QVVL1
0532_15
NOTES:
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/erase operations.
4. CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
5. RP# low transition is only to show t
RHPL
; not valid for above read and program cycles.
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.
7. V
PP
voltage during data program/erase operations valid at both 12.0V and 5.0V.
8. V
PP
voltage equal to or below V
PPLK
provides complete flash memory array protection.
Figure 16. AC Waveforms for CE
#
—Controlled Write Operations,
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read
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