
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
39
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19
R
Table 20:
Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Units
Speed Grade
-5
-4
Single-Ended Standards
GTL
0
0.02
ns
GTL_DCI
0.13
0.15
ns
GTLP
0.03
0.04
ns
GTLP_DCI
0.23
0.27
ns
HSLVDCI_15
1.51
1.74
ns
HSLVDCI_18
0.81
0.94
ns
HSLVDCI_25
0.27
0.31
ns
HSLVDCI_33
0.28
0.32
ns
HSTL_I
0.60
0.69
ns
HSTL_I_DCI
0.59
0.68
ns
HSTL_III
0.19
0.22
ns
HSTL_III_DCI
0.20
0.23
ns
HSTL_I_18
0.18
0.21
ns
HSTL_I_DCI_18
0.17
0.19
ns
HSTL_II_18
–0.02
–0.01
ns
HSTL_II_DCI_18
0.75
0.86
ns
HSTL_III_18
0.28
0.32
ns
HSTL_III_DCI_18
0.28
0.32
ns
LVCMOS12
Slow
2 mA
7.60
8.73
ns
4 mA
7.42
8.53
ns
6 mA
6.67
7.67
ns
Fast
2 mA
3.16
3.63
ns
4 mA
2.70
3.10
ns
6 mA
2.41
2.77
ns
LVCMOS15
Slow
2 mA
4.55
5.23
ns
4 mA
3.76
4.32
ns
6 mA
3.57
4.11
ns
8 mA
3.55
4.09
ns
12 mA
3.00
3.45
ns
Fast
2 mA
3.11
3.57
ns
4 mA
1.71
1.96
ns
6 mA
1.44
1.66
ns
8 mA
1.26
1.44
ns
12 mA
1.11
1.27
ns
LVDCI_15
1.51
1.74
ns
LVDCI_DV2_15
1.32
1.52
ns
LVCMOS18
Slow
2 mA
5.49
6.31
ns
4 mA
3.45
3.97
ns
6 mA
2.84
3.26
ns
8 mA
2.62
3.01
ns
12 mA
2.11
2.43
ns
16 mA
2.07
2.38
ns
Fast
2 mA
2.50
2.88
ns
4 mA
1.15
1.32
ns
6 mA
0.96
1.10
ns
8 mA
0.87
1.01
ns
12 mA
0.79
0.91
ns
16 mA
0.76
0.87
ns
LVDCI_18
0.81
0.94
ns
LVDCI_DV2_18
0.67
0.77
ns
LVCMOS25
Slow
2 mA
6.43
7.39
ns
4 mA
4.15
4.77
ns
6 mA
3.38
3.89
ns
8 mA
2.99
3.44
ns
12 mA
2.53
2.91
ns
16 mA
2.50
2.87
ns
24 mA
2.22
2.55
ns
Fast
2 mA
3.27
3.76
ns
4 mA
1.87
2.15
ns
6 mA
0.32
0.37
ns
8 mA
0.19
0.22
ns
12 mA
0
0
ns
16 mA
–0.02
–0.01
ns
24 mA
–0.04
–0.02
ns
LVDCI_25
0.27
0.31
ns
LVDCI_DV2_25
0.16
0.19
ns
Table 20:
Output Timing Adjustments for IOB
(Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Units
Speed Grade
-5
-4