
Spartan-3 FPGA Family: Functional Description
6
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DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
turing process. When the output driver turns off, the series
termination, by definition, approaches a very high imped-
ance; in contrast, parallel termination resistors remain at the
targeted values.
DCI is available only for certain I/O standards, as listed in
Table 6
. DCI is selected by applying the appropriate I/O
standard extensions to symbols or components. There are
five basic ways to configure terminations, as shown in
Table 7
. The DCI I/O standard determines which of these
terminations is put into effect.
Table 6:
DCI I/O Standards
Category of Signal
Standard
Signal Standard
V
CCO
(V)
For
Outputs
V
REF
for
Inputs (V)
Termination Type
For
Inputs
At Output
At Input
Single-Ended
Gunning
Transceiver Logic
GTL_DCI
1.2
1.2
0.8
Single
Single
GTLP_DCI
1.5
1.5
1.0
High-Speed
Transceiver Logic
HSTL_I_DCI
1.5
1.5
0.75
None
Split
HSTL_III_DCI
1.5
1.5
0.9
None
Single
HSTL_I_DCI_18
1.8
1.8
0.9
None
Split
HSTL_II_DCI_18
1.8
1.8
0.9
Split
HSTL_III_DCI_18
1.8
1.8
1.1
None
Single
Low-Voltage CMOS
LVDCI_15
1.5
1.5
-
Controlled impedance
driver
None
LVDCI_18
1.8
1.8
-
LVDCI_25
2.5
2.5
-
LVDCI_33
3.3
3.3
-
LVDCI_DV2_15
1.5
1.5
-
Controlled driver with
half-impedance
LVDCI_DV2_18
1.8
1.8
-
LVDCI_DV2_25
2.5
2.5
-
LVDCI_DV2_33
3.3
3.3
-
Stub Series
Terminated Logic
SSTL18_I_DCI
1.8
1.8
0.9
25-Ohm driver
Split
SSTL2_I_DCI
2.5
2.5
1.25
25-Ohm driver
SSTL2_II_DCI
2.5
2.5
1.25
Split with 25-Ohm driver
Differential
Low-Voltage
Differential
Signalling
LVDS_25_DCI
2.5
2.5
-
None
Split on
each line
of pair
LVDSEXT_25_DCI
2.5
2.5
-
Notes:
1.
Bank 5 of any Spartan-3 device in a VQ100 or TQ144 package does not support DCI signal standards.