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參數(shù)資料
| 型號(hào)： | XC3S1000-5CP132C |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | CSP-132 |
| 文件頁(yè)數(shù)： | 33/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-5CP132C |
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Spartan-3 FPGA Family: Functional Description
26
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
DFS Clock Output Connections
There are two basic cases that determine how to connect
the DFS clock outputs: on-chip and off-chip, which are illus-
trated in
Figure 15a
and
Figure 15c
, respectively. This is
similar to what has already been described for the DLL com-
ponent. See the
DLL Clock Output and Feedback Con-
nections
, page 22
section.
In the on-chip case, it is possible to connect either of the
DFS’s two output clock signals through general routing
resources to the FPGA’s internal registers. Either a Global
Clock Buffer (BUFG) or a BUFGMUX affords access to the
global clock network. The optional feedback loop is formed
in this way, routing CLK0 to a global clock net, which in turn
drives the CLKFB input.
In the off-chip case, the DFS’s two output clock signals, plus
CLK0 for an optional feedback loop, can exit the FPGA
using output buffers (OBUF) to drive a clock network plus
registers on the board. The feedback loop is formed by
feeding the CLK0 signal back into the FPGA using an
IBUFG, which directly accesses the global clock network, or
an IBUF. Then, the global clock net is connected directly to
the CLKFB input.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, there are nine clock outputs that employ the DLL to
achieve a desired phase relationship: CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and
CLKFX180. These outputs afford “coarse” phase control.
The second approach uses the PS component described in
this section to provide a still finer degree of control. The PS
component accomplishes this by introducing a "fine phase
shift" (T
PS
) between the CLKFB and CLKIN signals inside
the DLL component. The user can control this fine phase
shift down to a resolution of 1/256 of a CLKIN cycle or one
tap delay (DCM_TAP), whichever is greater. When in use,
the PS component shifts the phase of all nine DCM clock
output signals together. If the PS component is used
together with a DCM clock output such as the CLK90,
CLK180, CLK270, CLK2X180 and CLKFX180, then the fine
phase shift of the former gets added to the coarse phase
shift of the latter.
PS Component Enabling and Mode Selection
The CLKOUT_PHASE_SHIFT attribute enables the PS
component for use in addition to selecting between two
operating modes. As described in
Table 16
, this attribute
has three possible values: NONE, FIXED and VARIABLE.
When CLKOUT_PHASE_SHIFT is set to NONE, the PS
component is disabled and its inputs, PSEN, PSCLK, and
PSINCDEC, must be tied to GND. The set of waveforms in
Figure 17a
shows the disabled case, where the DLL main-
tains a zero-phase alignment of signals CLKFB and CLKIN
upon which the PS component has no effect. The PS com-
ponent is enabled by setting the attribute to either the
FIXED or VARIABLE values, which select the Fixed Phase
mode and the Variable Phase mode, respectively. These
two modes are described in the sections that follow
Determining the Fine Phase Shift
The user controls the phase shift of CLKFB relative to
CLKIN by setting and/or adjusting the value of the
PHASE_SHIFT attribute. This value must be an integer
ranging from –255 to +255. The PS component uses this
value to calculate the desired fine phase shift (T
PS
) as a
fraction of the CLKIN period (T
CLKIN
). Given values for
PHASE-SHIFT and T
CLKIN
, it is possible to calculate T
PS
as
follows:
T
PS
= (PHASE_SHIFT/256)*T
CLKIN
Both the Fixed Phase and Variable Phase operating modes
employ this calculation. If the PHASE_SHIFT value is zero,
then CLKFB and CLKIN will be in phase, the same as when
the PS component is disabled. When the PHASE_SHIFT
value is positive, the CLKFB signal will be shifted later in
time with respect to CLKIN. If the attribute value is negative,
the CLKFB signal will be shifted earlier in time with respect
to CLKIN.
(4)
The Fixed Phase Mode
This mode fixes the desired fine phase shift to a fraction of
the T
CLKIN
, as determined by Equation (4) and its
user-selected PHASE_SHIFT value P. The set of wave-
forms in
Figure 17b
illustrates the relationship between
CLKFB and CLKIN in the Fixed Phase mode. In the Fixed
Phase mode, the PSEN, PSCLK and PSINCDEC inputs are
not used and must be tied to GND.
Table 16:
PS Attributes
Attribute
Description
Values
CLKOUT_PHASE_SHIFT
Disables PS component or chooses between Fixed Phase
and Variable Phase modes.
NONE, FIXED, VARIABLE
PHASE_SHIFT
Determines size and direction of initial fine phase shift.
Integers from –255 to +255
(1)
Notes:
1.
The practical range of values will be less when T
> FINE_SHIFT_RANGE in the Fixed Phase mode, also when T
>
(FINE_SHIFT_RANGE)/2 in the Variable Phase mode. the FINE_SHIFT_RANGE represents the sum total delay of all taps.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC4000A | LAMP |
| XC4002A | Logic Cell Array Family |
| XC4003A | Logic Cell Array Family |
| XC4004A | Logic Cell Array Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CPG132C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CPG132I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5FG1156C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5FG1156I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan-3 FPGA |
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