
Spartan-3 FPGA Family: Pinout Descriptions
42
www.xilinx.com
DS099-4 (v1.6) January 17, 2005
Product Specification
R
PQ208 Footprint
Left Half of Package
(top view)
XC3S50
(124 max. user I/O)
I/O:
Unrestricted,
general-purpose user I/O
72
16
VREF:
User I/O or input
voltage reference for bank
17
N.C.:
Unconnected pins for
XC3S50 (
)
XC3S200, XC3S400
(141 max user I/O)
I/O:
Unrestricted,
general-purpose user I/O
83
22
VREF:
User I/O or input
voltage reference for bank
0
N.C.:
No unconnected pins
in this package
All devices
12
DUAL:
Configuration pin,
then possible user I/O
8
GCLK:
User I/O or global
clock buffer input
16
DCI:
User I/O or reference
resistor input for bank
7
CONFIG:
Dedicated
configuration pins
4
JTAG:
Dedicated JTAG
port pins
4
VCCINT:
Internal core
voltage supply (+1.2V)
12
VCCO:
Output voltage
supply for bank
8
VCCAUX:
Auxiliary voltage
supply (+2.5V)
28
GND:
Ground
Figure 11:
PQ208 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.
T
P
H
I
I
I
G
V
I
)
I
I
I
I
G
I
V
V
I
I
I
V
I
G
I
I
I
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GND
1
2
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
(
) IO_L16P_7/VREF_7
(
) IO_L16N_7
4
5
6
7
8
9
VCCO_7
IO_L19P_7
GND
IO_L19N_7/VREF_7
IO_L20P_7
IO_L20N_7
IO_L21P_7
IO_L21N_7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
GND
IO_L22P_7
IO_L22N_7
VCCA X
IO_L23P_7
IO_L23N_7
IO_L24P_7
IO_L24N_7
(
) IO_L39P_7
VCCO_7
(
) IO_L39N_7
U
GND
IO_L40P_7
IO_L40N_7/VREF_7
IO_L40P_6/VREF_6
IO_L40N_6
GND
(
) IO_L39P_6
VCCO_6
(
) IO_L39N_6
IO_L24P_6
IO_L24N_6/VREF_6
IO_L23P_6
IO_L23N_6
VCCAUX
IO_L22P_6
IO_L22N_6
GND
IO_L21P_6
IO_L21N_6
IO_L20P_6
IO_L20N_6
IO_L19P_6
GND
IO_L19N_6
VCCO_6
(
) IO/VREF_6
IO_L01P_6/VRN_6
IO_L01N_6/VRP_6
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
G
M
M
M
I
I
G
V
I
I
I
I
I
G
I
I
V
V
I
I
V
I
G
I
I
I
Bank 5
B
B
Bank 0
DS099-4_09a_121103
3