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參數(shù)資料
| 型號(hào)： | XC3S1000-5CP132C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | CSP-132 |
| 文件頁(yè)數(shù)： | 39/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-5CP132C |
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Spartan-3 FPGA Family: Functional Description
32
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
Configuration
Spartan-3 devices are configured by loading application
specific configuration data into the internal configuration
memory. Configuration is carried out using a subset of the
device pins, some of which are "Dedicated" to one function
only, while others, indicated by the term "Dual-Purpose",
can be re-used as general-purpose User I/Os once configu-
ration is complete.
Depending on the system design, several configuration
modes are supported, selectable via mode pins. The mode
pins M0, M1, and M2 are Dedicated pins. The mode pin set-
tings are shown in
Table 21
.
An additional pin, HSWAP_EN, is used in conjunction with
the mode pins to select whether user I/O pins have pull-ups
during configuration. By default, HSWAP_EN is tied High
(internal pull-up) which shuts off the pull-ups on the user I/O
pins during configuration. When HSWAP_EN is tied Low,
user I/Os have pull-ups during configuration. Other Dedi-
cated pins are CCLK (the configuration clock pin), DONE,
PROG_B, and the boundary-scan pins: TDI, TDO, TMS,
and TCK. Depending on the configuration mode chosen,
CCLK can be an output generated by the FPGA, or an input
accepting an externally generated clock.
A persist option is available which can be used to force the
configuration pins to retain their configuration function even
after device configuration is complete. If the persist option is
not selected then the configuration pins with the exception
of CCLK, PROG_B, and DONE can be used as user I/O in
normal operation. The persist option does not apply to the
boundary-scan related pins. The persist feature is valuable
in applications that readback configuration data after enter-
ing the User mode.
Table 22
lists the total number of bits required to configure
each FPGA as well as the PROMs suitable for storing those
bits. See
DS123
:
Platform Flash In-System Programmable
Configuration PROMs
data sheet for more information.
The Standard Configuration Interface
Configuration signals belong to one of two different catego-
ries: Dedicated or Dual-Purpose. Which category deter-
mines which of the FPGA’s power rails supplies the signal’s
driver and, thus, helps describe the electrical at the pin.
The Dedicated configuration pins include PROG_B,
HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and
M0-M2. These pins use the V
CCAUX
lines for power.
The Dual-Purpose configuration pins comprise INIT_B,
DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of
these pins, according to its bank placement, uses the V
CCO
lines for either Bank 4 (VCCO_4) or Bank 5 (VCCO_5). All
the signals used in the serial configuration modes rely on
VCCO_4 power. Signals used in the parallel configuration
modes and Readback require from VCCO_5 as well as from
VCCO_4.
Both the Dedicated and Dual-Purpose signals described
above constitute the configuration interface. In the standard
case, this interface is 2.5V-LVCMOS-compatible. This
means that 2.5V is applied to the V
CCAUX
, VCCO_4, and
VCCO_5 lines (this last in the parallel or Readback case
only). One need only apply 2.5 Volts to these V
CCO
lines
from power-on to the end of configuration. Upon entering
the User mode, it is possible to switch to supply voltage per-
mitting signal swings other than 2.5V.
Table 21:
Spartan-3 Configuration Mode Pin Settings
Configuration Mode
(1)
Master Serial
M0
0
M1
0
M2
0
Synchronizing Clock
CCLK Output
Data Width
1
Serial DOUT
(2)
Yes
Slave Serial
Master Parallel
1
1
1
1
1
0
CCLK Input
CCLK Output
1
8
Yes
No
Slave Parallel
JTAG
0
1
1
0
1
1
CCLK Input
TCK Input
8
1
No
No
Notes:
1.
2.
The voltage levels on the M0, M1, and M2 pins select the configuration mode.
The daisy chain is possible only in the Serial modes when DOUT is used.
Table 22:
Spartan-3 Configuration Data
Device
File Sizes
Xilinx Platform Flash PROM
Serial
Configuration
Parallel
Configuration
XC3S50
439,264
XCF01S
XCF08P
XC3S200
1,047,616
XCF01S
XCF08P
XC3S400
1,699,136
XCF02S
XCF08P
XC3S1000
3,223,488
XCF04S
XCF08P
XC3S1500
5,214,784
XCF08P
XCF08P
XC3S2000
7,673,024
XCF08P
XCF08P
XC3S4000
11,316,864
XCF16P
XCF16P
XC3S5000
13,271,936
XCF16P
XCF16P
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