- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374986 > XC3S1000-5CP132C (XILINX INC) Spartan-3 FPGA Family: Complete Data Sheet PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S1000-5CP132C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | CSP-132 |
| 文件頁(yè)數(shù)： | 51/198頁(yè) |
| 文件大小： | 1605K |
| 代理商： | XC3S1000-5CP132C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)
Spartan-3 FPGA Family: DC and Switching Characteristics
4
www.xilinx.com
DS099-3 (v1.5) December 17, 2004
Advance Product Specification
R
Table 5:
General Recommended Operating Conditions
Symbol
Description
Min
Nom
Max
Units
T
J
Junction temperature
Commercial
0
-
85
°
C
Industrial
–40
-
100
°
C
V
CCINT
V
CCO(1)
V
CCAUX(2)
Internal supply voltage
1.140
1.200
1.260
V
Output driver supply voltage
1.140
-
3.450
V
Auxiliary supply voltage
2.375
2.500
2.625
V
Notes:
1.
The V
range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended
V
range specific to each of the single-ended I/O standards is given in
Table 8
, and that specific to the differential standards is
given in
Table 10
.
Only during DCM operation, it is recommended that the rate of change of V
CCAUX
not exceed 10 mV/ms.
2.
Table 6:
General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Device
Revision
I
L(2)
Leakage current at User
I/O, Dual-Purpose, and
Dedicated pins
Future
Symbol
Description
Test Conditions
Min
Typ
Max
Units
μ
A
μ
A
μ
A
0
Driver is in a
high-impedance
state, V
IN
= 0V
or V
CCO
max,
sample-tested
V
CCO
> 3.0V
V
CCO
< 3.0V
All V
CCO
levels
–25
-
+25
–10
-
+10
–10
-
+10
I
RPU(3)
Current through pull-up
resistor at User I/O,
Dual-Purpose, and
Dedicated pins
All
V
IN
= 0V, V
CCO
= 3.3V
V
IN
= 0V, V
CCO
= 3.0V
V
IN
= 0V, V
CCO
= 2.5V
V
IN
= 0V, V
CCO
= 1.8V
V
IN
= 0V, V
CCO
= 1.5V
V
IN
= 0V, V
CCO
= 1.2V
V
IN
= V
CCO
–0.84
-
–2.35
mA
–0.69
-
–1.99
mA
–0.47
-
–1.41
mA
–0.21
-
–0.69
mA
–0.13
-
–0.43
mA
–0.06
-
–0.22
mA
I
RPD(3)
Current through
pull-down resistor at
User I/O, Dual-Purpose,
and Dedicated pins
All
0.37
-
1.67
mA
I
REF
V
REF
current per pin
0
V
CCO
> 3.0V
V
CCO
< 3.0V
All V
CCO
levels
–25
-
+25
μ
A
μ
A
μ
A
pF
–10
-
+10
Future
–10
-
+10
C
IN
Input capacitance
All
3
-
10
Notes:
1.
2.
The numbers in this table are based on the conditions set forth in
Table 5
.
The I
L
specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute V
IN
minimum and maximum values (
Table 1
). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages
within this range before applying V
CCO
power. Also consider applying V
CCO
power before the connection of data lines occurs. When
the FPGA is completely unpowered, the impedance at the I/O pins is high.
This parameter is based on characterization. The pull-up resistance R
PU
= V
CCO
/ I
RPU
. The pull-down resistance R
PD
= V
IN
/ I
RPD
.
Spartan-3 family values for both resistances are stronger than they have been for previous FPGA families.
3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC4000A | LAMP |
| XC4002A | Logic Cell Array Family |
| XC4003A | Logic Cell Array Family |
| XC4004A | Logic Cell Array Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CPG132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CPG132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5FG1156C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5FG1156I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。