
Spartan-3 FPGA Family: DC and Switching Characteristics
16
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DS099-3 (v1.5) December 17, 2004
Advance Product Specification
R
Table 17:
Input Timing Adjustments for IOB
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
Add the
Adjustment Below
Units
Speed Grade
-5
-4
Single-Ended Standards
GTL, GTL_DCI
0.44
0.50
ns
GTLP, GTLP_DCI
0.36
0.42
ns
HSLVDCI_15
0.51
0.59
ns
HSLVDCI_18
0.29
0.33
ns
HSLVDCI_25
0.51
0.59
ns
HSLVDCI_33
0.51
0.59
ns
HSTL_I, HSTL_I_DCI
0.51
0.59
ns
HSTL_III, HSTL_III_DCI
0.37
0.42
ns
HSTL_I_18,
HSTL_I_DCI_18
0.36
0.41
ns
HSTL_II_18,
HSTL_II_DCI_18
0.39
0.45
ns
HSTL_III_18,
HSTL_III_DCI_18
0.45
0.52
ns
LVCMOS12
0.63
0.72
ns
LVCMOS15
0.42
0.49
ns
LVDCI_15
0.38
0.43
ns
LVDCI_DV2_15
0.38
0.44
ns
LVCMOS18
0.24
0.28
ns
LVDCI_18
0.29
0.33
ns
LVDCI_DV2_18
0.28
0.33
ns
LVCMOS25
0
0
ns
LVDCI_25
0.05
0.05
ns
LVDCI_DV2_25
0.04
0.04
ns
LVCMOS33, LVDCI_33,
LVDCI_DV2_33
–0.05
–0.02
ns
LVTTL
0.18
0.21
ns
PCI33_3
0.20
0.22
ns
PCI66_3
0.18
0.20
ns
SSTL18_I, SSTL18_I_DCI
0.39
0.45
ns
SSTL2_I, SSTL2_I_DCI
0.40
0.46
ns
SSTL2_II, SSTL2_II_DCI
0.36
0.41
ns
Differential Standards
LDT_25 (ULVDS_25)
0.76
0.88
ns
LVDS_25, LVDS_25_DCI
0.65
0.75
ns
BLVDS_25
0.34
0.39
ns
LVDSEXT_25,
LVDSEXT_25_DCI
0.80
0.92
ns
LVPECL_25
0.18
0.21
ns
RSDS_25
0.43
0.50
ns
Notes:
1.
The numbers in this table are tested using the methodology
presented in
Table 21
and are based on the operating
conditions set forth in
Table 5
,
Table 8
, and
Table 10
.
These adjustments are used to convert input path times
originally specified for the LVCMOS25 standard to times that
correspond to other signal standards.
2.
Table 17:
Input Timing Adjustments for IOB
(Continued)
Convert Input Time from
LVCMOS25 to the
Following Signal Standard
Add the
Adjustment Below
Units
Speed Grade
-5
-4