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參數(shù)資料
| 型號(hào)： | XC3S1000-5CP132C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan-3 FPGA Family: Complete Data Sheet |
| 中文描述： | FPGA, 192 CLBS, 50000 GATES, PBGA132 |
| 封裝： | CSP-132 |
| 文件頁(yè)數(shù)： | 41/198頁(yè) |
| 文件大?。?/td> | 1605K |
| 代理商： | XC3S1000-5CP132C |
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Spartan-3 FPGA Family: Functional Description
34
www.xilinx.com
DS099-2 (v1.3) August 24, 2004
Preliminary Product Specification
40
R
Slave Serial mode is selected by applying <111> to the
mode pins (M0, M1, and M2). A pull-up on the mode pins
makes slave serial the default mode if the pins are left
unconnected.
Master Serial Mode
In Master Serial mode, the CCLK pin is an output pin. The
FPGA just to the right of the PROM in
Figure 20
is set for
Master Serial mode. It is the FPGA that drives the configu-
ration clock on the CCLK pin to a Xilinx Serial PROM which
in turn feeds bit-serial data to the DIN input. The FPGA
accepts this data on each rising CCLK edge. After the
FPGA has been loaded, the data for the next device in a
daisy-chain is presented on the DOUT pin after the falling
CCLK edge.
The interface is identical to slave serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a default frequency of 6 MHz.
Configuration bits then switch CCLK to a higher frequency
for the remainder of the configuration.
Slave Parallel Mode
The Parallel modes support the fastest configuration.
Byte-wide data is written into the FPGA with a BUSY flag
controlling the flow of data. An external source provides
8-bit-wide data, CCLK, an active-Low Chip Select (CS_B)
signal and an active-Low Write signal (RDWR_B). If BUSY
is asserted (High) by the FPGA, the data must be held until
BUSY goes Low. Data can also be read using the Slave
Parallel
mode. If RDWR_B is asserted, configuration data is
read out of the FPGA as part of a readback operation.
After configuration, it is possible to use any of the Multipur-
pose pins (DIN/D0-D7, DOUT/BUSY, INITB, CS_B, and
RDWR_B) as User I/Os. To do this, simply set the BitGen
option
Persist
to
No
and assign the desired signals to multi-
purpose configuration pins using the Xilinx development
software. Alternatively, it is possible to continue using the
configuration port (e.g. all configuration pins taken together)
when operating in the User mode. This is accomplished by
setting the
Persist
option to
Yes
.
Multiple FPGAs can be configured using the Slave Parallel
mode and can be made to start-up simultaneously.
Figure 21
shows the device connections. To configure mul-
tiple devices in this way, wire the individual CCLK, Data,
RDWR_B, and BUSY pins of all the devices in parallel. The
individual devices are loaded separately by deasserting the
CS_B pin of each device in turn and writing the appropriate
data.
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| XC3S1000-5CP132I | Spartan-3 FPGA Family: Complete Data Sheet |
| XC4000A | LAMP |
| XC4002A | Logic Cell Array Family |
| XC4003A | Logic Cell Array Family |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S1000-5CP132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5CPG132C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5CPG132I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family: Complete Data Sheet |
| XC3S1000-5FG1156C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
| XC3S1000-5FG1156I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA |
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