
CHAPTER 24 ROM CORRECTION FUNCTION
User
’
s Manual U15862EJ3V0UD
679
24.2.2 Correction control register (CORCN)
This register disables or enables the correction operation of correction address register n (CORADn) (n = 0 to 3).
Each channel can be enabled or disabled by this register.
This register is set by using an 8-bit or 1-bit memory manipulation instruction.
0
Disabled
Enabled
CORENn
0
1
Enables/disables correction operation
CORCN
0
0
0
COREN3 COREN2 COREN1 COREN0
After reset: 00H R/W Address: FFFFF880H
Remark
n = 0 to 3
Table 24-1. Correspondence Between CORCN Register Bits and CORADn Registers
CORCN Register Bit
Corresponding CORADn Register
COREN3
CORAD3
COREN2
CORAD2
COREN1
CORAD1
COREN0
CORAD0
24.3 ROM Correction Operation and Program Flow
<1>
If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by
the DBTRAP instruction.
When the DBTRAP instruction is executed, execution branches to address 00000060H.
Software processing after branching causes the result of ROM correction to be judged (the fetch address and
ROM correction operation are confirmed) and execution to branch to the correction software.
After the correction software has been executed, the return address is set, and return processing is started
by the DBRET instruction.
<2>
<3>
<4>
Cautions 1. The software that performs <3> and <4> must be executed in the internal ROM/RAM.
2. Develop the program so that the ROM correction function is not used until data has been
completely written to the CORCN register that controls ROM correction.
3. When setting an address to be corrected to the CORADn register, clear the higher bits to 0 in
accordance with the capacity of the internal ROM.
4. The ROM correction function cannot be used to correct the data of the internal ROM. It can
only be used to correct instruction codes. If ROM correction is used to correct data, that data
is replaced with the DBTRAP instruction code.