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型號(hào)：	UPD703214GFA1-xxx-JBT
廠商：	NEC Corp.
英文描述：	32-Bit Single-Chip Microcontrollers
中文描述：	32位單芯片微控制器
文件頁(yè)數(shù)：	352/757頁(yè)
文件大小：	4410K
代理商：	UPD703214GFA1-XXX-JBT

CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51

s Manual U15862EJ3V0UD

(1) 8-bit timer counters 50 and 51 (TM50, TM51)

The TM5n register is an 8-bit read-only register that counts the count pulses.

The counter is incremented in synchronization with the rising edge of the count clock.

Through cascade connection, the TM5n registers can be used as a 16-bit timer.

When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read

by a 16-bit memory manipulation instruction. However, because these registers are connected by an internal

8-bit bus, the TM50 register and TM51 register must be read divided into two times. Therefore, read these

registers twice and compare the values, taking into consideration that the reading occurs during a count

In the following cases, the count value becomes 00H.

When the TCE5n bit of 8-bit timer mode control register 5n (TMC5n) is cleared

The TM5n register and CR5n register match in the mode in which clear & start occurs on a match between

the TM5n register and 8-bit timer compare register 5n (CR5n)

When connected in cascade, these registers become 00H even when the TCE50 bit in the

lowest timer (TM50) is cleared.

(2) 8-bit timer compare registers 50 and 51 (CR50, CR51)

The CR5n register can be read and written by an 8-bit memory manipulation instruction.

In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count

value of 8-bit counter 5n (TM5n), and if the two values match, an interrupt request signal (INTTM5n) is

In the PWM mode, TM5n register overflow causes the TO5n pin output to change to the active level, and when

the values of the TM5n register and the CR5n register match, the TO5n pin output changes to the inactive

The value of the CR5n register can be set in the range of 00H to FFH.

When using the TM50 register and TM51 register in cascade as a 16-bit timer, the CR50 register and CR51

in 16-bit lengths, and if they match, an interrupt request (INTTM50) is generated.

Cautions 1. In the mode in which clear & start occurs upon a match of the TM5n register and CR5n

2. In the PWM mode, set the CR5n register rewrite interval to three or more count clocks

(clock selected with timer clock selection register 5n (TCL5n)).

3. Before changing the value of the CR5n register when using a cascade connection, be

sure to stop the timer operation.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UPD703214GFA2-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214GFA-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214GF-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214Y	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214YA	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers

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