
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO)
User
’
s Manual U15862EJ3V0UD
393
10.2 Configuration
RTO consists of the following hardware.
Table 10-1. Configuration of RTO
Item
Configuration
Registers
Real-time output buffer register n (RTBLn, RTBHn)
Control registers
Real-time output port mode register n (RTPMn)
Real-time output port control register n (RTPCn)
(1) Real-time output buffer register n (RTBLn, RTBHn)
RTBLn and RTBHn are 4-bit registers that hold output data in advance.
These registers are mapped to independent addresses in the peripheral I/O register area.
They can be read/written in 8-bit or 1-bit units.
If an operation mode of 4 bits
×
2 channels is specified (BYTEn = 0), data can be individually set to the RTBLn
and RTBHn registers. The data of both these registers can be read at once by specifying the address of either
of these registers.
If an operation mode of 6 bits
×
1 channel is specified (BYTEn = 1), 8-bit data can be set to both the RTBLn
and RTBHn registers by writing the data to either of these registers. Moreover, the data of both these registers
can be read at once by specifying the address of either of these registers.
Table 10-2 shows the operation when the RTBLn and RTBHn registers are manipulated.
0
RTBLn
RTBHn
0
RTBHn5 RTBHn4
RTBLn3
RTBLn2
RTBLn1
RTBLn0
After reset : 00H R/W Address :
RTBLn :
RTBHn :
FFFFF6E0H, FFFFF6F0
FFFFF6E2H, FFFFF6F2
Caution
When writing to bits 6 and 7 of the RTBHn register, always write 0.
Remark
n = 0, 1
n = 1 only for the V850ES/KJ1.
Table 10-2. Operation During Manipulation of Real-Time Output Buffer Registers n
Read
Write
Note
Operation Mode
Register to Be
Manipulated
Higher 4 bits
Lower 4 bits
Higher 4 bits
Lower 4 bits
RTBLn
RTBHn
RTBLn
Invalid
RTBLn
4 bits
×
1 channel, 2 bits
×
1 channel
RTBHn
RTBHn
RTBLn
RTBHn
Invalid
RTBLn
RTBHn
RTBLn
RTBHn
RTBLn
6 bits
×
1 channel
RTBHn
RTBHn
RTBLn
RTBHn
RTBLn
Note
After setting the real-time output port, set output data to the RTBLn and RTBHn registers by the time a real-
time output trigger is generated.