
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User
’
s Manual U15862EJ3V0UD
634
19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)
These registers set the interrupt mask status for maskable interrupts. Bits xxMKn of the IMR0 to IMR2 register and
bits xxMKn of the xxlCn register are respectively linked.
The IMRm register can be read/written in 16-bit units (m = 0 to 2).
When the higher 8 bits of the IMRm register are treated as the IMRmH register and the lower 8 bits of the IMRm
register as the IMRmL register, they can be read/written in 8-bit or 1-bit units (m = 0 to 2).
Caution
In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if
bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register,
is rewritten (as a result, the IMRm register is also rewritten).
(i) V850ES/KF1
CSI0MK1
PMK6
IMR0 (IMR0H
Note
)
(IMR0L)
CSI0MK0
PMK5
TM5MK1
PMK4
TM5MK0
PMK3
TM0MK11
PMK2
TM0MK10
PMK1
TM0MK01
PMK0
TM0MK00
WDT1MK
After reset: FFFFH R/W Address: FFFFF100H (IMR0, IMR0L), FFFFF101H (IMR0H)
After reset: FFFFH R/W Address: FFFFF102H (IMR1, IMR1L), FFFFF103H (IMR1H)
1
TMHMK1
IMR1 (IMR1H
Note
)
(IMR1L)
BRGMK
TMHMK0
WTMK
STMK1
WTIMK
SRMK1
KRMK
SREMK1
ADMK
STMK0
IICMK0
SRMK0
CSIAMK0
SREMK0
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
0
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
0
xxMKn
0
1
Enables interrupt servicing
Disables interrupt servicing
Interrupt mask flag setting
Note
When reading from or writing to bits 8 to 15 of the IMR0 and IMR1 registers in 8-bit or 1-
bit units, specify these bits as bits 0 to 7 of the IMR0H and IMR1H registers.
Caution
Bit 15 of the IMR1 register is fixed to 1. The operation is not generated if the
value is changed.
Remark
xx: Identifying name of each peripheral unit (CSI0, TM5, TM0, P, WDT, BRG, WT,
WTI, KR, AD, IIC, CSIA, TMH, ST, SR, SRE)
n: Peripheral unit number (See
Tables 19-5
to
19-7
.)