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型號(hào)：	UPD703214GFA1-xxx-JBT
廠商：	NEC Corp.
英文描述：	32-Bit Single-Chip Microcontrollers
中文描述：	32位單芯片微控制器
文件頁(yè)數(shù)：	614/757頁(yè)
文件大?。?/td>	4410K
代理商：	UPD703214GFA1-XXX-JBT

CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION

User’s Manual U15862EJ3V0UD

19.2 Non-Maskable Interrupts

Non-maskable interrupt requests are acknowledged unconditionally, even when interrupts are disabled (DI state).

Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt requests.

The following three types of non-maskable interrupt requests are available in the V850ES/KF1, V850ES/KG1, and

NMI pin input (NMI)

Non-maskable interrupt request due to overflow of watchdog timer 1 (INTWDT1)

Non-maskable interrupt request due to overflow of watchdog timer 2 (INTWDT2)

There are four choices for the valid edge of an NMI pin, namely: rising edge, falling edge, both edges, and no edge

The non-maskable interrupt due to overflow of watchdog timer 1 (INTWDT1) functions by setting the WDTN14 and

WDTM13 bits of watchdog timer mode register 1 (WDTM1) to 10.

The non-maskable interrupt due to overflow of watchdog timer 2 (INTWDT2) functions by setting the WDTN21 and

WDTM20 bits of watchdog timer mode register 1 (WDTM1) to 01.

When two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined

by the following priority order (the interrupt requests with low priority level are ignored).

INTWDT2 > INTWDT1 > NMI

If during NMI processing, an NMI, INTWDT1, or INTWDT2 request newly occurs, processing is performed as

(1) If an NMI request newly occurs during NMI processing

The new NMI request is held pending regardless of the value of the NP bit of the program status word (PSW)

of the CPU. The NMI request held pending is acknowledged upon completion of processing of the NMI

currently being executed (following RETI instruction execution).

(2) If an INTWDT1 request newly occurs during NMI processing

If the NP bit of PSW remains set (to 1) during NMI processing, the new INTWDT1 request is held pending. The

INTWDT1 request held pending is acknowledged upon completion of processing of the NMI currently being

executed (following RETI instruction execution).

If the NP bit of PSW is cleared (to 0) during NMI processing, a newly generated INTWDT1 request is executed

(NMI processing is interrupted).

(3) If an INTWDT2 request newly occurs during NMI processing

A newly generated INTWDT2 request is executed regardless of the value of the NP bit of PSW (NMI

processing is interrupted).

When a non-maskable interrupt request is generated, the PC and PSW values are saved to the

NMI occurrence status save registers (FEPC, FEPSW), but only NMIs can be restored via the

RETI instruction at this time. In the case of INTWDT1 and INTWDT2, restoration through the RETI

instruction is not possible, so perform system reset following completion of interrupt servicing.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
UPD703214GFA2-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214GFA-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
UPD703214GF-XXX-JBT	制造商:NEC 制造商全稱:NEC 功能描述:32-Bit Single-Chip Microcontrollers
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