
CHAPTER 22 RESET FUNCTION
User
’
s Manual U15862EJ3V0UD
673
Table 22-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2
Item
During Reset
After Reset
Main clock oscillator (f
X
)
Oscillation stops (f
X
= 0 level).
Oscillation starts
Subclock oscillator (f
XT
)
Oscillation can continue without effect from reset
Note
.
Peripheral clock (f
XX
to f
XX
/1024), internal
system clock (f
CLK
), CPU clock (f
CPU
)
Operation stops
Operation starts. However, operation
stops during oscillation stabilization time
count.
Watchdog timer 1 clock (f
XW
)
Operation stops
Operation starts
Internal RAM
Undefined if power-on reset occurs or writing data to RAM and reset conflict (data
loss); otherwise, retains values immediately before reset input.
I/O lines (ports)
High impedance
On-chip peripheral I/O registers
Initialized to specified status
Other on-chip peripheral functions
Operation stops
Operation can be started
Note
The on-chip feedback resistor is
“
connected
”
by default (refer to
6.3 (1) Processor clock control register
(PCC)
).
Table 22-2. Hardware Status on Occurrence of WDTRES1
Item
During Reset
After Reset
Main clock oscillator (f
X
)
Oscillation continues
Note
Subclock oscillator (f
XT
)
Oscillation can continue without effect from reset
Note
.
Peripheral clock (f
XX
to f
XX
/1024), internal
system clock (f
CLK
), CPU clock (f
CPU
)
Operation stops
Operation starts
Watchdog timer 1 clock (f
XW
)
Operation continues
Internal RAM
Undefined if writing data to RAM and reset conflict (data loss); otherwise, retains
values immediately before reset input.
I/O lines (ports)
High impedance
On-chip peripheral I/O registers
Initialized to specified status
Other on-chip peripheral functions
Operation stops
Operation can be started
Note
The on-chip feedback resistor is "connected" by default (refer to
6.3 (1) Processor clock control register
(PCC)
).