參數(shù)資料
型號(hào): UPD46128953-X
廠商: NEC Corp.
英文描述: 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述: 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁(yè)數(shù): 44/60頁(yè)
文件大小: 468K
代理商: UPD46128953-X
Preliminary Data Sheet M17506EJ1V1DS
44
μ
PD46128953-X
Figure 7-2. Burst Read Cycle Timing Chart (/CE1 Toggle Access)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
Q0
Q1
Q2
Q3
Q4
Q5
Q7
Q6
Q0
Q1
Q2
Q3
Q4
Q5
Add
Q6
Add
Q7
t
CLK
t
CH
t
CL
High-Z
t
CHCL
t
CHCL
t
CSV
t
CHV
t
AH
t
CES
t
OLZ
t
CSV
t
CHV
t
CEWA
t
WES
t
WEH
t
WES
t
WEH
t
ACS
t
ACH
t
ACS
t
ACH
t
CVCV
t
VPL
t
AH
t
VPL
t
CEWA
t
CWHZ
t
OES
t
OEH
t
OES
t
OES
t
AOS
t
AOS
Read Latency = 6
t
CHV
t
CHV
t
AC
t
HZ
t
HZ
t
AC
t
OH
t
OEH
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CLWA
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
t
OEH
t
CLWA
CLK (Input)
/ADV (Input)
/CE1 (Input)
/WAIT (Output)
/OE (Input)
A/DQ0 to A/DQ21 (Input/Output)
/WE (Input)
DQ22 to DQ31 (Output)
Remark
The above timing chart assumes read latency is set 6.
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