參數(shù)資料
型號(hào)： UPD46128953-X
廠商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁(yè)數(shù)： 4/60頁(yè)
文件大?。?/td> 468K
代理商： UPD46128953-X
Preliminary Data Sheet M17506EJ1V1DS
4
μ
PD46128953-X
Pin Function
(1/2)
Symbol
Description
A/DQ0 to A/DQ21
Synchronous address input/data input/output
These pins are used as address input pins and data input/output pins.
When they are used as address input pins, the input address is latched at the rising edge of CLK. When the
address is latched, the setup time and hold time must be satisfied at the rising edge of CLK.
When they are used as data input/output pins, the input data is latched at the rising edge of CLK. When
data is input, the setup time and hold time must be satisfied at the rising edge of CLK. Data is output from
these pins at the rising edge of CLK.
Synchronous data input/output.
While the A/DQ pins function as address input pins and data input/output pins, these pins function only as
data input/output pins.
The input data is latched at the rising edge of CLK. When data is input, the setup time and hold time must
be satisfied at the rising edge of CLK. Data is output at the rising edge of CLK.
Input clock.
Addresses and control signals are latched in synchronization with this signal.
All the synchronous input signals must satisfy the setup time and hold time at the rising edge of CLK.
Synchronous address valid input signal.
An address is latched at the rising edge of CLK while /ADV is LOW. When the address is latched, the setup
time and hold time must be satisfied at the rising edge of CLK.
Note: This signal serves as an asynchronous signal when the mode register set or read.
Synchronous chip enable input.
This device is active while /CE1 is LOW. When inputting /CE1, the setup time and hold time must be
satisfied at the rising edge of CLK.
Remark
This signal serves as an asynchronous signal when the mode register set or read.
Asynchronous power-down mode input
When this signal is made LOW, the device enters the power-down mode status.
CE2 is not synchronized with the clock. It is an asynchronous signal.
Synchronous output enable input.
When this signal is made LOW, read data is output.
When inputting /OE, the setup time and hold time must be satisfied at the rising edge of CLK.
Remark
This signal serves as an asynchronous signal when the mode register set or read.
Synchronous write enable input.
When /WE inputs a LOW at the same time as /ADV, the device recognizes a write operation. When inputting
/WE, the setup time and hold time must be satisfied at the rising edge of CLK.
Remark
This signal serves as an asynchronous signal when the mode register is set or read.
DQ22 to DQ31
CLK
/ADV
/CE1
CE2
/OE
/WE
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