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參數(shù)資料
| 型號(hào)： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁(yè)數(shù)： | 28/60頁(yè) |
| 文件大小： | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
28
μ
PD46128953-X
Table 4-6. AC Specification of Mode Register Setting / Reading
Item
Symbol
-E12X, -E15X
Unit
MIN.
MAX.
Specification of Mode Register Setting / Reading
Cycle time
t
MSC
90
10000
ns
Address setup time to /ADV = HIGH
t
AS
6
ns
Address hold time to /ADV = HIGH
t
AH
1
ns
/CE1 setup time to /ADV = HIGH
t
CS
6
ns
Address setup time to /OE = LOW
t
AOSM
0
ns
/ADV Low pulse width
t
VPL
6
ns
/OE to output in low impedance
t
OLZM
5
ns
/OE to output valid
t
ACM
30
ns
/CE1 to output in high impedance
t
CHZM
10
ns
/OE to output in high impedance
t
OHZM
10
ns
Write data setup time to /WE = HIGH
t
DW
20
ns
Write data hold time to /WE = HIGH
t
DH
0
ns
/CE1 HIGH pulse width
t
CP
10
ns
/WE LOW pulse width
t
WP
50
ns
/OE LOW pulse width
t
OVL
50
ns
For the timing chart and flowchart, refer to
Figure 8-1. Mode Register Setting Timing Chart
,
Figure 8-2. Mode
Register Setting Flowchart
,
Figure 8-3. Mode Register Read Timing Chart
and
Figure 8-4. Mode Register Read
Flowchart
.
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