參數(shù)資料
型號(hào): UPD46128953-X
廠商: NEC Corp.
英文描述: 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION
中文描述: 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍
文件頁數(shù): 23/60頁
文件大?。?/td> 468K
代理商: UPD46128953-X
Preliminary Data Sheet M17506EJ1V1DS
23
μ
PD46128953-X
4. Mode Register Settings
The default value of the mode register of the
μ
PD46128953-X is undefined upon power application. Therefore, be sure
to set the mode register after power application and initialization.
4. 1 Mode Register Setting Method
Each mode can be set by performing a total of six cycles of operations in succession after reading the most significant
address (3FFFFFH) – two consecutive cycles for writing any data and three consecutive cycles for writing specific data
(codes 1 to 3) – by an asynchronous access (with CLK fixed HIGH or LOW).
Table 4-1. Mode Register Settings
Cycle
Operation
Address
Data
1st cycle
Read
3FFFFFH
Don’t care
2nd cycle
Write
3FFFFFH
Don’t care
3rd cycle
Write
3FFFFFH
Don’t care
4th cycle
Write
3FFFFFH
Code 1 (A/DQ0 = 1)
5th cycle
Write
3FFFFFH
Code 2
6th cycle
Write
3FFFFFH
Code 3
Codes 1 to 3 are set at the register. The register has a function to latch an address and data necessary for instruction
execution, and does not occupy the memory.
Whether the mode register is set or read can be selected by code 1 in the 4th bus cycle. If setting of the mode register
is selected (A/DQ0 = 1) by code 1 in the 4th bus cycle, the contents of the mode register are set by code 2 in the 5th bus
cycle and code 3 in the 6th bus cycle.
The command contents are shown in
Table 4-2. Mode Register Code 1 Definition (4th cycle)
,
Table 4-3. Mode
Register Code 2 Definition (5th cycle)
, and
Table 4-4. Mode Register Code 3 Definition (6th cycle)
.
For the timing chart and flowchart, refer to
Figure 8-1. Mode Register Setting Timing Chart
and
Figure 8-2. Mode
Register Setting Flowchart
.
If reading the mode register is selected by code 1 in the 4th bus cycle (A/DQ = 0), the contents of the mode register
currently set in the 5th and 6th bus cycles can be read. If the mode register is read before it is set, any (undefined) data
is read.
For the mode register, refer to
4.2 Mode Register Reading
.
4. 1. 1
Cautions for Setting Mode Register
When the mode register is set, the status of the internal counter is identified by the toggle operation of /CE1 and /OE.
When setting a mod entry, therefore, perform a toggle operation of /CE1 in each cycle (one read cycle and five write
cycles).
In the 1st bus cycle (read cycle), perform a toggle operation of /OE in the same manner as /CE1. If an illegal address
or data is written or if an address and data are written in an incorrect sequence, the mode register is not correctly set.
If the most significant address (3FFFFFH) is read (in the 1st bus cycle), written (2nd bus cycle), and then written (3rd
bus cycle), a sequence of setting/reading the mode register is started. Therefore, setting of the mode register cannot be
stopped after the 4th bus cycle. If the normal sequence is executed up to the 5th bus cycle, setting of the mode register
cannot be stopped until the 6th bus cycle is completed.
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