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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復用溫度范圍 |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
21
μ
PD46128953-X
3. 8 /WAIT signal behavior
/WAIT is a status signal (output) that indicates the preparation for starting burst read/burst write
This pin outputs a LOW while the internal circuit is busy, and a HIGH when it is ready.
The wait signal is output at the rising edge of CLK.
Table 3-2. Relation Between Internal Operation of Memory and /WAIT Output
Internal Operation of Memory
/WAIT output
Preparation for burst read/burst write in progress
LOW
Completion of preparation for burst read/burst write
HIGH
3. 9 /WAIT output
The /WAIT output is enabled after specified time from CLK. /WAIT output is transferred LOW to HIGH one cycle before
1st burst read data output and 1st burst write data input.
Figure 3-7. /WAIT Output Timing (Read Cycle)
T0
/ADV (Input)
CLK (Input)
T1
T2
T3
T4
A/DQ0 to A/DQ21 (Input/Output)
High-Z
Q0
Read Latency = 6
/WAIT (Output)
DQ22 to DQ31 (Output)
High-Z
Q0
Add
T5
T6
1 cycle before latency cycle
t
CEWA
t
CLWA
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