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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復用溫度范圍 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
19
μ
PD46128953-X
3. 6 Burst Read Termination
A burst read termination is executed when /CE1 is made HIGH during a burst read operation. The command that the
burst read termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the read data is
output before the command of the burst read termination (/CE1 = HIGH) is input.
Figure 3-5. Burst Read Termination
T4
T5
T6
CLK (Input)
/CE1 (Input)
/OE (Input)
A/DQ0-A/DQ21 (Output)
High-Z
T7
T8
T9
T10
t
CES
DQ22-DQ31 (Output)
Q0
Q1
Q2
Q3
Q4
L
/ADV (Input)
H
t
CEH
t
AC
t
HZ
High-Z
Q0
Q1
Q2
Q3
Q4
Remark
If the burst read termination is performed (/CE1: LOW
→
HIGH) before the rising edge of CLK in T8, as
shown in
Figure 3-5
, determined data is output as the read data (Q4) from the rising edge of CLK in T7.
The burst read termination is valid after the initial read data has been output.
(For the burst read termination, refer to
Figure 7-5. Burst Read Termination Cycle Timing Chart (/CE1 control)
.)
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