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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 29/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
29
μ
PD46128953-X
5. Address, /OE, /WE, DM control
5. 1 Relation of address inputs and /OE control
This product uses only one pin to input an address and input/output DQ. Consequently, a bus fight may occur between
an address input from the controller and data output from the memory and, therefore, the timing must be considered.
Data is output after specified t
OLZ
from the first rising edge of CLK when /OE has changes its level from HIGH to LOW.
Therefore, complete inputting an address from the controller before the first rising edge of CLK when /OE has changed
its level from HIGH to LOW.
Figure 5-1. Address inputs and /OE Timing
T0
T1
T2
CLK (Input)
/CE1 (Input)
/OE (Input)
A/DQ0 to A/DQ21 (Input/Output)
T3
T4
T5
T6
t
OES
DQ22 to DQ31 (Output)
High-Z
Q0
Q1
Q2
/ADV (Input)
t
OEH
Add
t
OLZ
t
AH
t
AOS
t
ACH
Read Latency = 6
High-Z
Q0
Q1
Q2
T7
T8
Remark
Refer to
6. Electrical Specifications
,
7. Timing Charts
in detail of AC specification.
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