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參數(shù)資料
| 型號： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
20
μ
PD46128953-X
3. 7 Burst Write Termination
A burst write termination is executed when /CE1 is made HIGH during a burst write operation. The command that the
burst write termination (/CE1 = HIGH) is recognized at the next rising edge of CLK when /CE1 = HIGH, the write data is
written before the command of the burst write termination (/CE1 = HIGH) is input.
Figure 3-6. Burst Write Termination
T3
T4
T5
CLK (Input)
/CE1 (Input)
/WE (Input)
A/DQ0 to A/DQ21 (Input)
High-Z
T6
T7
T8
T9
DQ22 to DQ31 (Input)
D0
D1
D2
/ADV (Input)
H
t
WDS
t
WDH
t
CES
t
CEH
D3
D4
D5
High-Z
D0
D1
D2
D3
D4
D5
Remark
If the burst write termination is performed (/CE1: LOW
→
HIGH) before the rising edge of CLK in T8, as
shown in
Figure 3-6
, the write data is input to memory at the rising edge of CLK in T7. The write data input
in cycle T8 (D5) is invalid.
The burst termination is valid after the initial write data has been input.
(For the burst write termination refer to
Figure 7-6. Burst Write Termination Cycle Timing Chart (/CE1 control)
.)
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