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參數(shù)資料
| 型號(hào)： | UPD46128953-X |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-BIT CMOS MOBILE SPECIFIED RAM 4M-WORD BY 32-BIT ADDRESS / DATA MULTIPLEXED EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 128兆位CMOS移動(dòng)指明內(nèi)存分詞由32位地址/數(shù)據(jù)復(fù)用溫度范圍 |
| 文件頁(yè)數(shù)： | 35/60頁(yè) |
| 文件大?。?/td> | 468K |
| 代理商： | UPD46128953-X |
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Preliminary Data Sheet M17506EJ1V1DS
35
μ
PD46128953-X
5. 4. 2
/OE LOW to HIGH during burst read operation
The output is controlled depending on the status of /OE (HIGH or LOW) when CLK rises. As shown in Figure 5-9, if
/OE is made from HIGH to LOW before the rising edge of CLK in T8 during burst read, the read data (Q5) output from the
rising edge of CLK in T8 is output. Because /OE = HIGH until cycle T7, the read data (Q0, Q1, Q2, Q3, and Q4) that
should be output when /OE = LOW are not output, but go into a high impedance state.
Figure 5-9. /OE LOW to HIGH during burst read operation Timing
T4
T5
T6
T7
T8
T9
T10
t
OES
t
OEH
H
L
t
OAC
t
OLZ
High-Z
High-Z
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK (Input)
/CE1 (Input)
/OE (Input)
A/DQ0 to A/DQ21 (Output)
DQ22 to DQ31 (Output)
/ADV (Input)
Remark
Refer to
6. Electrical Specifications
,
7. Timing Charts
in detail of AC specification.
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